Multi-chip Package Vertical Stacking Signal Length Reduction
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Solution Overview
Problem
Conventional multi-chip package structures require through openings in substrates, leading to increased signal transmission lengths, complex manufacturing processes, and higher production costs, while also complicating size reduction and heat dissipation.
Innovation Solution
A multi-chip package structure where a second chip is positioned between the substrate and the first chip, eliminating the need for substrate openings, with bumps and contacts arranged to ensure electrical connectivity and heat dissipation, and allowing for independent testing of package modules before assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If through openings are fabricated in the substrate to accommodate stacked chips, then chip integration is achieved, but signal transmission length increases and electrical performance deteriorates
Solution Approach 1:
The patent transitions from planar substrate routing to three-dimensional vertical stacking, where chips are stacked in the Z-direction and connected through vertical vias. This dimensional change allows signals to travel shorter vertical distances rather than long horizontal paths around openings, resolving the contradiction between integration and signal length.
Solution Approach 2:
The patent implements nested stacking where multiple chips are vertically stacked and embedded within the substrate structure. The chips are positioned at different height levels and connected through conductive vias that pass through intermediate substrate layers, creating a compact nested configuration that reduces overall package footprint while maintaining short signal paths.
2Adaptability or versatility
If through openings are fabricated in the substrate, then chip stacking is enabled, but manufacturing complexity and production cost increase
Solution Approach 1:
The patent divides the substrate into multiple discrete layers with conductive vias formed in each layer. Instead of creating single complex through-openings, the manufacturing process is segmented into sequential steps of forming vias and conductive structures in individual substrate layers, which can then be stacked and interconnected. This segmentation simplifies each manufacturing step while achieving the overall chip stacking goal.
3Adaptability or versatility
If substrate perimeter is increased to accommodate openings and routing, then chip stacking is achieved, but overall package size increases
Solution Approach 1:
The patent exploits the third dimension (vertical stacking) to achieve chip integration without expanding the horizontal footprint. By stacking chips vertically and connecting them through vertical vias, the package achieves high integration density while maintaining a compact footprint, directly resolving the contradiction between stacking capability and package size.
4Adaptability or versatility
If conventional substrate opening design is used, then chip integration is achieved, but heat dissipation becomes difficult
Solution Approach 1:
The patent introduces thermal vias and heat dissipation structures as intermediary elements between the stacked chips and the substrate. These conductive thermal pathways act as mediators to efficiently conduct heat away from the chips through the substrate, resolving the heat dissipation problem while maintaining the integrated stacking configuration.
Data Source
AI summary
A multi-chip package structure is provided with a first chip, a substrate adjacent to the first chip, a plurality of contacts connecting the first chip and the substrate, a second chip disposed between the first chip and the substrate and connecting to the first chip, and a underfill film, wherein the underfill film covers the contact to isolate the contact from the second chip, wherein an empty space is defined by the second chip and the substrate so that the second chip does not contact the substrate.