Multi-chip Package with Vertical Conductive Vias
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Solution Overview
Problem
Existing multi-chip packaging technologies face challenges in achieving high component density and optimal electrical connections, particularly with wire bonding methods that occupy space and restrict design, and in Package-on-Package techniques where costs are high and electrical properties are suboptimal for radio-frequency signals.
Innovation Solution
A multi-chip package design where at least one component is attached with its contact terminals facing the conductor pattern, allowing for shorter contact elements that connect directly to the conductor pattern, reducing space usage and improving electrical properties by using a conductor pattern and insulation structure with contact elements extending mainly in the thickness direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect components to the package structure, then electrical connections can be established, but the wire connections occupy space and restrict the design of the package geometry
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional vertical connections using conductive vias through the substrate. Contact elements extend vertically from the first component through the substrate to connect with the second component, utilizing the thickness dimension rather than lateral space, thereby reducing package area while maintaining connection reliability
Solution Approach 2:
The substrate serves as an intermediary structure that hosts both components and provides integrated conductive pathways. Instead of separate wire bonds acting as intermediaries, the substrate itself with embedded vias and conductor patterns acts as the mediating structure, eliminating the need for discrete wire connections and reducing overall package footprint
2Quantity of substance
If Package-on-Package technique is used with multiple packages stacked, then component density increases, but costs become high due to multi-stage packaging process and electrical properties are suboptimal for radio-frequency signals
Solution Approach 1:
The patent merges multiple functions into a single integrated substrate structure: mechanical support for both components, electrical interconnection through vias, signal routing through conductor patterns, and RF signal transmission pathways. This consolidation eliminates the need for separate packaging stages and intermediate boards, reducing process complexity while maintaining high component density
Solution Approach 2:
The substrate performs multiple functions simultaneously: it serves as the mounting platform for both components, provides vertical interconnection through conductive vias, offers lateral signal routing through conductor patterns, and enables RF signal transmission with optimized electrical properties. This multi-functionality reduces the number of discrete packaging operations required
3Quantity of substance
If two components are placed on top of each other on the same substrate using flip-chip technique, then vertical integration is achieved, but the placing and connection of the upper component becomes very difficult requiring wire-connection technology around the components
Solution Approach 1:
Conductive vias are formed in the substrate before components are mounted. This preliminary preparation of vertical connection pathways allows subsequent component placement to be straightforward, as the electrical connections are already in place within the substrate. The first component is connected to pre-formed vias, and the second component connects to the same or different vias, eliminating the need for post-placement wire bonding
Data Source
AI summary
Manufacturing method and a multi-chip package, which comprises a conductor pattern and insulation, and, inside the insulation, a first component, the contact terminals of which face towards the conductor pattern and are conductively connected to the conductor pattern. The multi-chip package also comprises inside the insulation a second semiconductor chip, the contact terminals of which face towards the same conductor pattern and are conductively connected through contact elements to this conductor pattern. The semiconductor chips are located in such a way that the first semiconductor chip is located between the second semiconductor chip and the conductor pattern.