Multi-Chip Package Structure for Hybrid Bonding and Warpage Control
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Solution Overview
Problem
The integration of multiple semiconductor devices into a single package poses challenges in manufacturing, particularly in achieving efficient hybrid bonding and heat dissipation while minimizing warpage and redistribution layer stress, which affects the yield and performance of electronic devices.
Innovation Solution
The method involves hybrid bonding of semiconductor wafers and chips using fusion bonding and thermal treatment, along with the integration of through semiconductor vias and insulating encapsulants to form a system-on-integrated chip (SOIC) structure, which includes the use of dummy chips for heat dissipation and alignment of conductive vias to reduce thermal expansion mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor devices are integrated into a single package, then device functionality and performance are improved, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent divides the integration process into distinct stages: wafer-level hybrid bonding of through-silicon via (TSV) structures, followed by singulation into individual chips, and subsequent packaging. This segmentation allows each stage to be optimized independently, reducing overall manufacturing complexity while achieving multi-device integration.
Solution Approach 2:
The patent performs preliminary hybrid bonding and TSV formation at the wafer level before singulation. This preliminary action enables multiple devices to be prepared and bonded in advance, simplifying the final packaging process and reducing manufacturing complexity.
2Reliability
If hybrid bonding is used to integrate multiple chips, then electrical performance is improved, but warpage and redistribution layer stress increase
Solution Approach 1:
The patent introduces dummy chips with specific thermal and mechanical properties at strategic locations within the package. These dummy chips provide local quality adjustments to compensate for thermal expansion mismatches and stress concentrations, thereby reducing warpage while maintaining electrical performance of the functional chips.
Solution Approach 2:
The patent modifies material parameters and structural configurations of the redistribution layers and bonding interfaces to reduce thermal expansion mismatch. By changing these parameters, the patent minimizes warpage and stress while preserving the electrical performance benefits of hybrid bonding.
3Temperature
If through semiconductor vias are integrated for heat dissipation, then thermal management is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms through-silicon via (TSV) structures and performs hybrid bonding at the wafer level before singulation. This preliminary action ensures that TSV alignment is established when the wafer provides a stable reference plane, reducing the precision requirements compared to aligning TSVs in individual chips after fabrication.
Solution Approach 2:
The patent uses the wafer itself as an intermediary substrate during the TSV formation and bonding process. This intermediary approach provides a stable platform that simplifies alignment and reduces the manufacturing precision requirements for TSV integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical performance and heat dissipation of integrated circuits, reduces warpage and redistribution layer stress, and increases the yield by ensuring proper alignment and bonding of semiconductor components.
Implementation Method 1
hybrid bonding of semiconductor wafers and chips using fusion bonding
Implementation Method 2
using fusion bonding and thermal treatment
Implementation Method 3
integration of through semiconductor vias and insulating encapsulants to form a system-on-integrated chip (SOIC) structure, which includes the use of dummy chips for heat dissipation
Implementation Method 4
alignment of conductive vias to reduce thermal expansion mismatch
Data Source
AI summary
A package includes a first package structure and a second package structure stacked on and electrically connected to the first package structure. The first package structure includes an integrated circuit, conductive structures, and an encapsulant. The integrated circuit includes a first chip, a second chip, a third chip, and a fourth chip. The first chip includes a semiconductor substrate. The second and the third chips are disposed side by side on the first chip. The fourth chip is disposed over the first chip and includes a semiconductor substrate. Sidewalls of the semiconductor substrate of the first chip are aligned with sidewalls of the semiconductor substrate of the fourth chip. The encapsulant laterally encapsulates the integrated circuit and the conductive structures. A topmost surface of the encapsulant is coplanar with top surfaces of the conductive structures. A bottommost surface of the encapsulant is coplanar with bottom surfaces of the conductive structures.