Multi-Chip Package Power Ball Layout for Peak Current Reduction
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Solution Overview
Problem
The integration of multiple chips in a single package can lead to excessively high peak currents, causing system instability and abnormal operation due to severe internal voltage drops, potentially resulting in system crashes.
Innovation Solution
The solution involves connecting a smaller number of chips to each Vcc and Vss packaging ball, using multiple power sources, and distributing the load across multiple Vcc and Vss packaging balls to reduce peak currents, thereby stabilizing the system operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If all chips are connected to the same power supply positive pole (Vcc) and power supply negative pole (Vss), then the packaging structure is simple and easy to manufacture, but excessively high peak currents occur causing system instability and abnormal operation
Solution Approach 1:
The power supply connection is segmented by dividing chips into different groups, where each group is connected to separate power supply packaging balls. Specifically, first chips are connected to first power supply packaging balls while second chips are connected to second power supply packaging balls, preventing all chips from sharing the same power supply path and thereby reducing peak current concentration.
2Quantity of substance
If multiple chips are integrated in a single package to save space and enhance performance, then high integration and space savings are achieved, but peak currents become excessively high causing severe internal voltage drops and system crashes
Solution Approach 1:
The integration of multiple chips is maintained while segmenting the power supply connections. Different groups of integrated chips are connected to different power supply packaging balls, which divides the current path and reduces the peak current magnitude that any single power supply path must handle, thereby preventing severe voltage drops.
Solution Approach 2:
Different power supply connections are provided for different groups of chips within the same package. The first power supply packaging balls are specifically connected to first chips while second power supply packaging balls are connected to second chips, creating localized power supply paths tailored to specific chip groups to manage current distribution.
3Ease of manufacture
If all chips share the same power supply connection to simplify the packaging structure, then manufacturing is easier, but internal voltage drops become severe leading to system crashes and abnormal states
Solution Approach 1:
The power supply connection structure is segmented into multiple independent paths. Instead of all chips connecting to a single power supply packaging ball, the structure divides chips into groups that connect to different power supply packaging balls, maintaining manufacturing simplicity while preventing severe voltage drops through distributed current paths.
Data Source
AI summary
The application discloses a multi-chip packaging structure, a method for reducing peak current and a semiconductor device. A plurality of chips are packed on a substrate. A plurality of packaging balls are embedded on the substrate, connected to a plurality of power sources. A plurality of connection nodes are packed on the substrate to connect the packaging balls to the chips. The power sources include a plurality of first power sources and second power sources. The packaging balls include a plurality of first packaging balls and second packaging balls, with the first packaging balls connected to the first power sources and the second packaging balls connected to the second power sources. The first packaging balls are connected to a part of the chips through the connection nodes.