Multi-Chip Power Assembly With Wafer-Level Low-Inductance Interconnect
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Solution Overview
Problem
Conventional power converter and inverter applications with half-bridge configurations experience increased power losses due to high loop inductance resulting from metal clips and wire bonds connecting separate power transistor dies, necessitating a reduction in loop inductance.
Innovation Solution
The method involves processing semiconductor wafers into separated dies, reversing or replacing their orientations, and securing them with a dielectric material to achieve direct source-drain connections via wafer-level metallization, reducing loop inductance by minimizing the gap between dies to less than 70 μm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal clips and wire bonds are used to connect separate power transistor dies, then the dies can be electrically connected, but loop inductance increases
Solution Approach 1:
The patent merges the electrical connection function into the wafer-level metallization layer, eliminating separate metal clips and wire bonds. The continuous metallization layer directly connects adjacent dies through the substrate, combining mechanical support and electrical connection into a single integrated structure that minimizes loop inductance and power losses.
Solution Approach 2:
The substrate acts as an intermediary element that enables direct electrical connection between adjacent dies. The metallization layer formed on the substrate serves as the mediating conductive path, replacing traditional wire bonds and metal clips with a low-inductance intermediate connection structure.
2Ease of manufacture
If separate dies are connected at package level, then manufacturing is simpler, but loop inductance increases
Solution Approach 1:
The patent performs electrical interconnection at the wafer level before die separation, rather than after packaging. The metallization layer is formed and patterns are created while dies are still on the wafer, establishing low-inductance connections in advance. This preliminary action integrates connection fabrication into the existing wafer manufacturing process, avoiding additional package-level assembly steps.
Solution Approach 2:
The patent replaces the mechanical assembly process of connecting separate packaged dies with a wafer-level semiconductor fabrication process. Instead of mechanical wire bonding or clip attachment, the electrical connections are created through deposited and patterned metallization layers that are inherently low-inductance due to their planar geometry and direct routing.
3Loss of energy
If wafer-level processing is used to reduce gap between dies, then loop inductance decreases, but manufacturing complexity increases
Solution Approach 1:
The patent uses universal wafer-level fabrication techniques (deposition, patterning, etching) that are already standard in semiconductor manufacturing. The same equipment and process tools used for creating transistor structures are employed to form the interconnect metallization layers, adding no specialized or complex equipment requirements to the manufacturing line.
Solution Approach 2:
The patent changes the spatial parameter of die separation by keeping dies in close proximity on the wafer during processing, rather than separating them into individual packages. This parameter change (maintaining small gap distances) is achieved through the wafer-level process geometry itself, where the substrate and metallization layers naturally maintain close spacing between adjacent die regions without requiring additional alignment or positioning steps.
Data Source
AI summary
A multi-chip assembly includes: a first power transistor die having a source terminal facing a first direction and a drain terminal facing a second direction opposite the first direction; and a second power transistor die having a drain terminal facing the first direction, and a source terminal facing the second direction. A dielectric material occupies a gap between the first power transistor die and the second power transistor die, and secures the first power transistor die and the second power transistor die to one another. A metallization connects the source terminal of the first power transistor die to the drain terminal of the second power transistor die at a same side of the multi-chip assembly. The gap occupied by the dielectric material is less than 70 μm. Corresponding methods of producing multi-chip assemblies are also described.