Multi-Chip Power Semiconductor Package for Synchronized Switching
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Solution Overview
Problem
Existing power semiconductor devices face challenges in efficiently operating multiple chips in parallel within a package, particularly in ensuring simultaneous control and load terminal connections for high current and voltage applications.
Innovation Solution
A power semiconductor device with a package housing multiple chips, where each chip has load and control terminals connected through outside terminals, allowing for parallel operation with individual control signal distribution to ensure synchronized switching, and a lead frame structure for electrical connections, enabling efficient high-voltage and high-current handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple power semiconductor chips are integrated within a package to handle high current and voltage applications, then the power handling capability is improved, but the complexity of ensuring simultaneous control and synchronized switching increases
Solution Approach 1:
The package is segmented into multiple independent chip modules, each with its own control terminal and load terminals. This segmentation allows each chip to be controlled independently while maintaining synchronized switching through common control signals, thereby managing the complexity of multi-chip coordination.
Solution Approach 2:
The package structure provides universal connectivity where multiple chips share common external load terminals (first and second outside terminals) while maintaining individual control terminals. This multi-functional architecture enables the package to handle high power through parallel chip operation while simplifying control through standardized terminal connections.
2Productivity
If multiple chips are connected in parallel within a package, then the current handling capability is improved, but the difficulty of ensuring simultaneous control and load terminal connections increases
Solution Approach 1:
Multiple chips are merged within a single package structure, sharing common external load terminals while maintaining individual control terminals. This merging approach consolidates the current handling capability of multiple chips into one package, simplifying the external connections while enabling parallel operation for enhanced current capacity.
3Adaptability or versatility
If individual control terminals are provided for each chip within the package, then the adaptability for synchronized switching is improved, but the number of external connections and device complexity increases
Solution Approach 1:
The control architecture is segmented to provide individual control terminals for each chip, enabling independent control signals to be applied to each device. This segmentation enhances adaptability for synchronized switching while the integrated package structure manages the complexity of multiple connections.
Data Source
AI summary
A power semiconductor device includes: a package and a plurality of power semiconductor chips, each power semiconductor chip including a semiconductor body, a first load terminal, a second load terminal and a control terminal. The device also includes a plurality of outside terminals. The outside terminals include: one or more first outside terminals electrically connected with the first load terminals; one or more second outside terminals each of which is electrically connected with each of the second load terminals; and a plurality of third outside terminals. Each control terminal is electrically connected with at least one individual third outside terminal of the plurality of third outside terminals.