Multi-Chip Pulse Width Calibration for Process Variation
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Solution Overview
Problem
Process variation in semiconductor transistors leads to signal distortion during communication between chips in multi-chip systems, necessitating an innovative signal monitoring and calibration design to address this issue.
Innovation Solution
A multi-chip system with a monitoring and calibration system that estimates and records the pulse width of input signals, allowing for calibration of chip settings to mitigate signal distortion, where test data is used to transmit output signals through chip-to-chip connections and processed by subsequent chips to identify and correct pulse width deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If process variation in semiconductor transistors is present during chip fabrication, then chip output performance varies, but signal distortion occurs in communication between chips
Solution Approach 1:
The patent applies preliminary action by performing pulse width calibration before actual signal transmission. The system pre-characterizes each chip's pulse width response and stores calibration data in lookup tables, so that when signals are transmitted, the appropriate calibration parameters are already available to compensate for process variation-induced distortion.
Solution Approach 2:
The patent implements feedback by measuring the actual pulse width at the receiving chip and using this information to adjust transmission parameters. The system monitors signal quality and dynamically selects calibration parameters from lookup tables to compensate for detected distortions, creating a closed-loop system that adapts to process variations.
2Productivity
If more chips are connected in series to enhance computing power, then system capability increases, but signal distortion accumulates
Solution Approach 1:
The patent applies segmentation by dividing the multi-chip system into individual calibration units, where each chip has its own pulse width characteristics stored in a lookup table. This allows the system to handle each chip-link interface independently with specific calibration parameters, preventing error accumulation across the series connection.
Solution Approach 2:
The patent uses parameter changes by dynamically adjusting pulse width calibration parameters based on the number and configuration of chips in the system. The lookup tables store multiple calibration parameter sets that can be selected based on system configuration, allowing optimization for different numbers of series-connected chips.
3Reliability
If pulse width calibration is performed for each chip connection, then signal distortion is eliminated, but system complexity increases
Solution Approach 1:
The patent reduces complexity by performing calibration measurements once during manufacturing or initialization and storing the results in lookup tables. This preliminary characterization eliminates the need for complex real-time calibration circuits, as the system simply retrieves pre-computed parameters during operation.
Solution Approach 2:
The patent uses copying by creating lookup tables that store calibrated pulse width parameters for different chip configurations. Instead of implementing complex real-time calculation circuits, the system copies appropriate calibration parameters from these tables based on the actual system configuration, simplifying the hardware design.
Data Source
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AI summary
A multi-chip system includes a plurality of chips and a monitoring and calibration system. The plurality of chips include at least a first chip and a second chip, wherein an output port of the first chip is connected to an input port of the second chip via a chip-to-chip connection, the first chip transmits an output signal to the second chip via the chip-to-chip connection, and the second chip processes an input signal that is derived from the output signal transmitted via the chip-to-chip connection. The monitoring and calibration system calibrates a chip setting of at least one of the first chip and the second chip for pulse width calibration of the input signal.