Multi-Chip RAM Clock Transmission With Gated Rank Wake-Up
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Solution Overview
Problem
In memory devices with stacked chips, the delay in matching a stack identifier (stackID) with a chip identifier (chipID) complicates the enabling of a clock after detecting a specific command target, leading to impractical or impossible clock transmission at the appropriate time due to long propagation and decoding delays, especially in modes like gear down or power down.
Innovation Solution
Implementing a gated clock topology that partitions clock logic between ranks, allowing initial clock enabling on a base chip and subsequent waking of clocks for other ranks, reducing delay by decoupling clock transmission from chip/stack ID matching delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the clock is enabled after detecting a specific command target, then the clock transmission timing is improved, but the delay in matching stackID with chipID causes the clock enabling to be impractical or impossible
Solution Approach 1:
The patent divides the clock logic into separate components: a clock enable generator that produces the initial clock enable signal, and a clock distributor that receives and distributes the clock signal to multiple memory chips. This segmentation allows the clock enabling process to be decoupled from the stackID matching delay, making timely clock transmission possible despite the identification delay
Solution Approach 2:
The clock enable generator produces the clock enable signal in advance based on detecting a specific command target, before the stackID matching is complete. This preliminary action allows the clock to be enabled early, and the signal is then distributed to the appropriate chips after their identifiers are matched, resolving the timing conflict
2Reliability
If the clock runs freely most of the time, then the clock is always available, but power consumption increases
Solution Approach 1:
The patent implements dynamic clock management where the clock signal is enabled and disabled based on operational needs. The clock enable generator produces enable signals only when specific command targets are detected, and the clock distributor distributes the clock signal accordingly. This dynamic approach ensures the clock is available when needed while consuming minimal power during idle periods
Solution Approach 2:
The clock signal is activated periodically or event-driven rather than continuously. The clock enable generator triggers clock distribution based on detected command targets, creating periodic or event-based clock activation patterns that maintain reliability while reducing overall power consumption compared to continuous free-running operation
Data Source
AI summary
Devices and methods include a first memory chip including first memory banks, a command input configured to receive a command and a chip identifier, and a decoder configured to determine whether the command is to use a clock on the second memory chip when the command matches predetermined conditions. The devices and methods also include a second memory chip including second memory banks and a clock receiver configured to receive the clock from the first memory chip to be used in memory operations on the second memory chip. The first memory chip acts a base chip for a stack of memory chips that includes the first memory chip and the second memory chip. When the command matches the predetermined conditions, the first memory chip is configured to send the chip identifier to the second memory chip to the clock receiver to activate the clock receiver before transmitting the command to the second memory chip.