Multi-Chip Interconnection Package with Sacrificial Pattern Alignment

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The existing multi-chip short-distance interconnection solutions face manufacturing accuracy issues, preventing the creation of finer interconnection lines and thereby limiting data transmission bandwidth.

Innovation Solution

A chip interconnection package method involving a sacrificial pattern layer, an interconnection winding pattern layer, and insulating layers, where the sacrificial pattern layer defines opening positions for interconnections, allowing for precise alignment and communication between multiple chips through interconnection holes and conductive material.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If existing multi-chip interconnection solutions are used, then manufacturing process is simpler, but interconnection line width cannot be reduced below current limits due to manufacturing accuracy problems

Engineering Contradiction:

Improveinterconnection line width precisionVSAvoidpackage structure complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent divides the interconnection structure into multiple segments: support structure, sacrificial pattern layer, interconnection winding pattern layer, insulating layers, and chip layers. This segmentation allows each component to be manufactured and positioned independently with standard precision, while the overall structure achieves finer effective interconnection line widths through the winding pattern design.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The sacrificial pattern layer is formed in advance before the interconnection winding pattern layer. This preliminary action creates a template that guides the subsequent formation of the interconnection structure, enabling precise positioning and alignment without requiring direct manufacturing of fine interconnection lines at the final stage.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If finer interconnection lines are manufactured, then data transmission bandwidth increases, but manufacturing accuracy requirements become unattainable with existing solutions

Engineering Contradiction:

Improvedata transmission bandwidthVSAvoidinterconnection line manufacturing accuracy

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The sacrificial pattern layer acts as an intermediary that enables the formation of fine interconnection structures. By using this temporary template layer, the patent achieves precise interconnection line positioning and width control without directly manufacturing fine lines, thus bypassing the manufacturing accuracy limitations while enabling higher data transmission bandwidth.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent transitions from planar interconnection lines to a three-dimensional winding pattern structure. The interconnection winding pattern layer wraps around the sacrificial pattern, creating effective fine-pitch interconnections through vertical and horizontal winding. This dimensional transformation allows achieving fine effective line pitch without requiring equivalent manufacturing precision in the deposition process.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Measurement precision

If support structure is removed to achieve precise alignment, then interconnection accuracy improves, but structural stability during manufacturing decreases

Engineering Contradiction:

Improveinterconnection hole alignment accuracyVSAvoidpackage structure stability

Core Design Contradiction:

Measurement precisionVSStability of the object's composition

Solution Approach 1:

The sacrificial pattern layer is formed and used as a stable reference structure before the support structure is removed. This preliminary formation of the sacrificial pattern provides a stable template for subsequent alignment operations, and only after this reference is established is the support structure removed to achieve final precision alignment.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The support structure is selectively removed after it has served its purpose as a temporary carrier. The sacrificial pattern layer remains as the permanent reference structure, allowing the support structure to be extracted without compromising the stability of the alignment reference needed for precise interconnection hole formation.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS12112956B2Chip interconnection package structure and method

Publication Date: 2024.10.08 SHENZHEN XIUYUAN ELECTRONICS TECH CO LTD

AI summary

Provided are a chip interconnection package structure and method, including: forming a sacrificial pattern layer on a support structure; forming an interconnection winding pattern layer on the sacrificial pattern layer, wherein the interconnection winding pattern layer is corresponding to a sacrificial pattern of the sacrificial pattern layer in position; forming a first insulating layer on the interconnection winding pattern layer; forming a plurality of chips arranged at intervals on the first insulating layer, wherein the plurality of chips are respectively corresponding to the interconnection winding pattern of the interconnection winding pattern layer in position; and removing the support structure, and forming, on one side of the sacrificial pattern layer, a first interconnection hole penetrating through the sacrificial pattern, the interconnection winding pattern and the first insulating layer, and making the first interconnection hole aligned and communicated with a first interconnection pin of the chip corresponding in projection position.