Multichip Package Shoreline Layout for Offloaded Memory Interfaces
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Solution Overview
Problem
Integrated circuit packages with multiple dies face challenges in accommodating high-performance input-output components, such as external memory interfaces and bulk RAM, which compete for limited space on the main die, leading to bandwidth and clock source issues, and are hindered by the need to keep pace with rapidly changing memory standards, resulting in design complexity and time-to-market delays.
Innovation Solution
Offloading external memory interface (EMIF) and bulk RAM components onto an expansion tile within the same package, allowing the main die to focus on core fabric performance while decoupling memory standards and scaling independently, and using universal interface blocks to communicate with the expansion tile and high-bandwidth memory modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If external memory interface (EMIF) and bulk RAM components are placed on the main die, then memory interface functionality is integrated, but shoreline space is limited and design flexibility is reduced
Solution Approach 1:
The patent divides the memory interface functionality into two separate components: the EMIF controller remains on the main die, while the bulk RAM is offloaded to a separate memory device. This segmentation allows the main die to maintain its shoreline space for other I/O components while still providing integrated memory interface functionality.
Solution Approach 2:
The patent extracts the bulk RAM from the main die and places it on a separate memory device within the same package. This extraction frees up valuable shoreline space on the main die while maintaining the integrated memory interface capability through the universal interface block.
2Adaptability or versatility
If multiple I/O components are placed on the main die, then functionality is integrated, but bandwidth and clock source issues arise
Solution Approach 1:
The patent implements a universal interface block that can dynamically configure the data path width (x8, x16, x32) and support multiple memory interface standards. This universal interface handles both the EMIF controller and bulk RAM operations, simplifying bandwidth and clock source management while maintaining integrated functionality.
Solution Approach 2:
The interface block is designed to be dynamically reconfigurable, allowing the data path width and interface mode to be adjusted based on the specific memory device connected. This dynamic capability enables the system to adapt to different memory configurations without increasing device complexity.
3Speed
If memory standards are kept current on the main die, then performance is optimized, but design complexity and time-to-market increase
Solution Approach 1:
The patent introduces a separate memory device as an intermediary that handles the implementation of current memory standards. The main die only needs to provide the universal interface block, while the memory device contains the standard-specific logic, reducing design complexity on the main die while maintaining optimized performance.
Solution Approach 2:
The patent segments the memory standard implementation into two parts: the universal interface block on the main die and the standard-specific logic on the separate memory device. This segmentation allows the main die to remain relatively simple while still supporting current memory standards through the paired memory device.
Data Source
AI summary
A multichip package may include at least a main die mounted on a substrate. The main die may be coupled to one or more transceiver dies also mounted on the substrate. The main die may include one or more universal interface blocks configured to interface with an on-package memory device or an on-package expansion die, both of which can be mounted on the substrate. The expansion die may include external memory interface (EMIF) components for communicating with off-package memory devices and/or bulk random-access memory (RAM) components for storing large amounts of data for the main die. Smaller input-output blocks such as GPIO (general purpose input-output) or LVDS (low-voltage differential signaling) interfaces may be formed within the core fabric of the main die without causing routing congestion while providing the necessary clock source.