Multi-Chip Package Layout for Shorter Inter-Chip Signal Paths
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Solution Overview
Problem
Current semiconductor packaging technologies face limitations in achieving high-performance and efficient signal communication between multiple semiconductor chips, leading to suboptimal overall performance due to constrained signal transmission speeds.
Innovation Solution
A multi-chip package design incorporating a redistribution circuit structure, conductive posts, and encapsulants to electrically connect semiconductor chips, reducing the signal transmission path length and enhancing communication efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional multi-chip package technology is used to integrate multiple semiconductor chips, then the package achieves thin and light volume, but the signal communication speed between chips is limited
Solution Approach 1:
The patent transitions from conventional planar chip arrangement to a three-dimensional stacked configuration where semiconductor chips are vertically positioned above and below the redistribution circuit structure. This dimensional change enables direct vertical electrical connection through conductive posts, significantly shortening signal transmission paths and improving communication speed while maintaining a compact package footprint.
Solution Approach 2:
The patent introduces a redistribution circuit structure as an intermediary component that facilitates direct electrical connection between upper and lower semiconductor chips. This intermediary structure, equipped with conductive posts, enables high-speed signal transmission by providing dedicated vertical connection pathways, resolving the speed limitation of conventional multi-chip packages without requiring overly complex direct chip-to-chip coupling.
2Speed
If multiple semiconductor chips are integrated into a single package, then the overall package performance should improve, but the signal transmission path length remains too long
Solution Approach 1:
The patent employs vertical stacking of semiconductor chips in the third dimension, with the redistribution circuit structure positioned between upper and lower chips. This spatial reconfiguration transforms horizontal signal routing into vertical connections through conductive posts, dramatically reducing the signal transmission path length and enabling faster communication between chips.
3Reliability
If direct electrical connection between chips is implemented through conductive posts, then signal transmission quality improves, but the manufacturing precision requirements increase
Solution Approach 1:
The patent implements preliminary alignment features during the manufacturing process, where the redistribution circuit structure is pre-configured with conductive posts at predetermined positions. This preliminary action establishes accurate reference points before chip assembly, ensuring proper alignment between conductive posts and chip bonding pads, thereby achieving reliable electrical connections while managing manufacturing precision requirements.
Data Source
AI summary
A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.