Multi-chip Stack Package with Copper Wiring Substrate
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional multi-chip stack packages face signal delay due to unequal lengths of bonding wires and require costly redistribution layers with narrow gold circuits, leading to high fabrication costs and inefficient signal transmission.
Innovation Solution
A multi-chip stack package design that eliminates the need for additional redistribution layers by using a second wiring substrate with copper circuits, where the first and second chips are connected through conductive bumps and solder balls, ensuring equal signal transmission paths and reducing fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional multi-chip stack package uses bonding wires to connect chips to wiring substrate, then electrical connection is achieved, but signal delay occurs due to unequal wire lengths and re-routing
Solution Approach 1:
The patent removes the bonding wire connection method and replaces it with direct solder ball connections from chips to the wiring substrate. This extraction of the bonding wire intermediate layer eliminates the re-routing problem and unequal length variations that cause signal delay, while maintaining electrical connectivity through the solder balls that directly attach to pads on the wiring substrate.
Solution Approach 2:
The patent segments the connection function by using separate solder balls for different signal paths, allowing each connection to be independently optimized. The wiring substrate is designed with multiple pads arranged to accommodate chips with different bonding pad configurations, enabling each chip to connect through its own dedicated solder balls without requiring re-routing through other chips' connection paths.
2Adaptability or versatility
If redistribution layer with gold circuits is used to arrange bonding pads, then electrical connection flexibility is improved, but fabrication cost increases due to expensive gold material and clean room requirements
Solution Approach 1:
The patent replaces the expensive gold redistribution layer with a cost-effective solder ball connection system. Instead of using precious metal circuits on the chip, the invention uses readily available solder balls that are cheaper and can be applied through standard reflow soldering processes without requiring clean room facilities, significantly reducing manufacturing costs while maintaining connection flexibility.
Solution Approach 2:
The patent changes the material parameter from gold to solder, and the process parameter from clean room fabrication to standard reflow soldering. This parameter change maintains the electrical connection function while dramatically reducing fabrication costs and simplifying the manufacturing process, making the package more economically viable without sacrificing adaptability.
3Manufacturing precision
If redistribution layer is formed on all wafer areas, then complete chip coverage is achieved, but wafer utilization decreases when only partial areas need redistribution
Solution Approach 1:
The patent applies partial action by forming solder balls only on the specific areas of the chip where bonding pads require external connections. Instead of covering the entire chip surface, the solder ball array is configured to match only the necessary connection points, allowing unused chip areas to remain functional for other purposes and improving overall wafer utilization while maintaining complete coverage where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances signal transmission efficiency and lowers fabrication costs by using copper circuits with wider dimensions, avoiding signal delay and reducing the need for clean room fabrication, while improving wafer utilization.
Implementation Method 1
The solder balls are disposed on an under surface of the wiring substrate to be away from a front side of the second chip 130... electrically connected to a first conductive channel 112 of the wiring substrate 110
Implementation Method 2
Each of the first bonding pads 122 of the first chip 120 is electrically connected to a first conductive channel 112 of the wiring substrate 110 via one of the first bonding wires 140
Data Source
AI summary
A multi-chip stack package comprising a first wiring substrate, a first chip, a second wiring substrate, and a second chip is provided. The first wiring substrate is with a front side and a rear side. The first chip is disposed on the front side of the first wiring substrate and electrically connected to the first wiring substrate and the first chip has a first active surface. The second wiring substrate is disposed on the first active surface of the first chip and electrically connected to the first wiring substrate. The second chip is disposed on the second wiring substrate and electrically connected to the second wiring layer. The second active surface of the second chip faces the first active surface of the first chip.