Multi-Chip Stack Coupling Filter for Low-Power Signal Transmission
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Solution Overview
Problem
Current two-dimensional integrated circuit technologies face limitations in increasing density and signal transmission efficiency due to physical constraints and increased interconnections, prompting the need for efficient signal transmission methods between chips.
Innovation Solution
A multi-chip stack structure utilizing a series capacitor and magnetically coupled inductance coils to form a coupling filter, enabling wireless transmission between chips with improved transmission coefficients and energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional integrated circuit technology is used to increase integration density, then more components can be integrated into a given area, but the number and length of interconnections increase significantly, causing increased circuit RC delay and power consumption
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking of chips. Multiple chips are stacked vertically with interconnections made through the thickness direction, enabling signals to reach destination chips more directly without traversing long lateral paths, thereby reducing RC delay and power consumption while maintaining high integration density
2Quantity of substance
If more devices are put into one chip to increase integration density, then more components can be integrated, but more complex designs are required
Solution Approach 1:
The patent divides a large-scale integrated circuit into multiple smaller functional modules distributed across separate chips. Each chip contains a subset of devices and interconnections, reducing the complexity of individual chip designs while achieving high overall integration density through vertical stacking and inter-chip communication
3Quantity of substance
If the number and length of interconnections increase to support more devices, then more devices can be integrated, but circuit RC delay increases
Solution Approach 1:
The patent uses vertical stacking to create short inter-chip connection paths through the thickness direction. This three-dimensional approach reduces the length of interconnections compared to lateral routing in two-dimensional layouts, thereby reducing RC delay and improving signal transmission speed while supporting a larger number of devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances communication quality and reduces energy consumption by increasing the transmission coefficient, allowing for efficient wireless data transmission over longer distances with improved energy efficiency.
Implementation Method 1
The second inductance coil is magnetically coupled with the first inductance coil
Implementation Method 2
The first chip includes a first series capacitor and a first inductance coil, where the first series capacitor connected to the first inductance coil in series
Data Source
AI summary
A multi-chip stack structure and a signal transmission method are disclosed in specification and drawing, where the multi-chip stack structure includes first and second chips. The first chip includes a first inductance coil with a first series capacitor, and the second chip includes a second inductance coil with a second series capacitor. The first and second inductance coils are magnetically coupled to each other. The magnetically coupled inductance coils and the capacitors constitute a coupling filter.