Multi-Chip Stack Fabrication Using Film Over Wire Insulation
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Solution Overview
Problem
Current multi-chip stack structures face challenges such as increased package area and height, wire bonding difficulties, short circuits, and high process costs due to long bonding wires and complex fabrication processes, which hinder the development of small-sized, thin-type electronic devices.
Innovation Solution
A method involving a chip carrier with a first chip group stacked in a step-like manner, a second chip connected to the carrier, and a third chip stacked with an insulative film between the first and second chips to prevent bonding wire contact, reducing the number of layers and height, and using a film over wire technique to simplify the process and reduce wire length and arc height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more memory chips are stacked to increase memory capacity, then the memory capacity increases, but the projecting area of the entire structure continuously increases causing the memory chips to go out of the packageable range
Solution Approach 1:
The patent transitions from a planar side-by-side chip arrangement to a three-dimensional vertical stack structure. Multiple memory chips are stacked in the vertical dimension rather than expanding horizontally, allowing increased memory capacity within a compact footprint that remains within packageable range.
Solution Approach 2:
The patent implements a nested arrangement where multiple memory chips are vertically stacked one on top of another, with each chip positioned within the vertical envelope of the structure below it. This nesting approach maximizes space utilization and keeps the overall projecting area compact.
2Reliability
If the controller chip is electrically connected to the chip carrier through bonding wires, then electrical connection is achieved, but the bonding wires contact the memory chips below causing short circuit problems
Solution Approach 1:
The patent introduces an insulative film as an intermediary layer between the bonding wires and the memory chips. This film acts as a mediator that allows the bonding wires to pass through vertically while preventing direct contact with the memory chip surfaces, thereby eliminating short circuit risks while maintaining electrical connectivity.
Solution Approach 2:
The patent employs a thin insulative film that is flexible enough to accommodate the bonding wire routing while providing effective electrical insulation. This thin film structure allows the bonding wires to pass through without contacting the memory chips, preventing short circuits while maintaining reliable electrical connections.
3Reliability
If long bonding wires are used to connect chips in a vertical stack, then chip connectivity is achieved, but the wire length and arc height increase leading to high process costs and wire sweep problems
Solution Approach 1:
The patent changes the bonding wire routing from horizontal paths to vertical paths by stacking chips vertically. This dimensional change significantly reduces the wire length and arc height required for inter-chip connections, eliminating wire sweep problems and reducing process costs while maintaining reliable chip connectivity.
4Ease of manufacture
If chips are arranged in a step-like manner for wire bonding, then wire bonding process is facilitated, but the package area and height increase
Solution Approach 1:
The patent adopts a vertical stack arrangement where chips are positioned one above another in the vertical dimension, rather than arranging them in a step-like horizontal pattern. This vertical stacking facilitates wire bonding by allowing direct vertical wire routing while minimizing both package area and height, thereby reducing overall package volume.
Data Source
AI summary
A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficultly.