Multi-Chip Stack Using Through-Chip Vias to Eliminate Spacers

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Solution Overview

Problem

Conventional multi-chip packaging methods using wire bonding result in increased size, mechanical durability issues, thermal resistance, and electrical performance reduction due to the need for spacers and longer bond wires, leading to unreliable and inefficient chip stacking.

Innovation Solution

The use of through-chip vias for both parallel and serial connections between chips, allowing for symmetric pad arrangements and eliminating the need for spacers, thereby reducing the size and improving signal integrity by creating short interconnects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If wire bonding technology is used for chip stacking, then chip connections can be established, but package size increases and mechanical durability decreases

Engineering Contradiction:

Improvemechanical durabilityVSAvoidpackage size

Core Design Contradiction:

ReliabilityVSVolume of stationary object

Solution Approach 1:

The patent extracts and eliminates the spacer component from the chip stacking structure. By removing the spacer that was necessary for wire bonding, the invention enables direct chip-to-chip contact, reducing package size while improving mechanical durability by eliminating the fragile wire-bonding arrangement that required spacer support.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the mechanical wire bonding system with a direct electrical contact system through aligned bonding pads. This substitution eliminates the need for bonding wires and spacers, thereby reducing package size and improving mechanical durability by removing the odd-angle wire attachments that weakened the structure.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Ease of operation

If spacers are used in wire bonding chip stacks, then chip positioning is enabled, but height increases and handling becomes more challenging

Engineering Contradiction:

Improvehandling easeVSAvoidstack height

Core Design Contradiction:

Ease of operationVSLength of stationary object

Solution Approach 1:

The patent removes the spacer component entirely from the chip stacking architecture. By extracting this element, the stack height is reduced and handling becomes simpler, as the compact structure without protruding spacers is easier to manipulate and assemble.

Inventive Principle:

Principle #2Taking out (Extraction)

3Reliability

If longer bond wires are used in chip stacks with spacers, then chip connections are maintained, but electrical performance decreases

Engineering Contradiction:

Improveelectrical performanceVSAvoidbond wire length

Core Design Contradiction:

ReliabilityVSLength of moving object

Solution Approach 1:

The patent replaces the long bond wire connection system with a direct pad-to-pad electrical contact system. By eliminating the bonding wires entirely and using aligned bonding pads for direct contact, the electrical path length is minimized, thereby improving electrical performance through reduced inductance, capacitance, and resistance.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Temperature

If spacers are included in integrated device stacks, then chip spacing is provided, but thermal resistance increases

Engineering Contradiction:

Improvethermal resistanceVSAvoidstack structure

Core Design Contradiction:

TemperatureVSVolume of stationary object

Solution Approach 1:

The patent extracts and removes the spacer component from the stack structure. This elimination creates direct thermal contact between chips, removing the thermal barrier that spacers introduced, thereby reducing thermal resistance and improving heat dissipation while maintaining a compact volume.

Inventive Principle:

Principle #2Taking out (Extraction)

5Reliability

If conventional bonding wire methods are used, then chip connections are established, but electrical shorts occur during assembly

Engineering Contradiction:

Improveproduction yieldVSAvoidassembly process

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent replaces the bonding wire assembly process with a direct pad alignment and contact process. This substitution eliminates the steps of applying spacer material and positioning chips on spacers, which were sources of electrical shorts. The new method aligns bonding pads directly with corresponding pads on adjacent chips, removing the assembly steps that caused shorting issues and improving production yield.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS8383514B2Method for stacking serially-connected integrated circuits and multi-chip device made from same

Publication Date: 2013.02.26 MOSAID TECH

AI summary

A multi-chip device and method of stacking a plurality substantially identical chips to produce the device are provided. The multi-chip device, or circuit, includes at least one through-chip via providing a parallel connection between signal pads from at least two chips, and at least one through-chip via providing a serial or daisy chain connection between signal pads from at least two chips. Common connection signal pads are arranged symmetrically about a center line of the chip with respect to duplicate common signal pads. Input signal pads are symmetrically disposed about the center line of the chip with respect to corresponding output signal pads. The chips in the stack are alternating flipped versions of the substantially identical chip to provide for this arrangement. At least one serial connection is provided between signal pads of stacked and flipped chips when more than two chips are stacked.