Multi-Chip Timer Synchronization Using Bidirectional Sampling
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Solution Overview
Problem
In systems with multiple interconnected chips, maintaining accurate timer synchronization is challenging due to unknown or varying propagation delays over interconnect wires, leading to inconsistencies and errors in timer values across chips.
Innovation Solution
A method involving synchronized sampling of timer values between primary and secondary chips, calculating a correction value based on the differences in timer values, and applying it immediately to synchronize the secondary timers, accounting for signal propagation delays in both directions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the primary chip periodically transmits its timer value to secondary chips over interconnect wires, then timer synchronization is maintained across chips, but propagation delay variations cause errors in timer values
Solution Approach 1:
The patent introduces a delay measurement mechanism as an intermediary component that measures the actual propagation delay of timing signals between chips. This measured delay value acts as a mediator to compensate for the timing errors caused by interconnect wire variations, thereby resolving the contradiction between maintaining synchronization and avoiding measurement errors.
Solution Approach 2:
The system implements a feedback mechanism where the measured propagation delay is continuously fed back to adjust the timer values on secondary chips. This feedback loop allows the system to dynamically compensate for delay variations, ensuring accurate timer synchronization despite changes in interconnect conditions.
2Measurement precision
If propagation delay over interconnect wires is unknown or variable, then timer synchronization becomes inaccurate, but measuring and compensating for delay adds system complexity
Solution Approach 1:
The system employs self-service by having the chips themselves perform the delay measurement using their existing timer circuitry and interconnect structures. Rather than requiring external measurement equipment, the chips use their own resources to measure and compensate for propagation delays, reducing overall system complexity while maintaining measurement precision.
3Stability of the object's composition
If the primary timer is corrected between transmissions, then synchronization drift is reduced, but secondary chips experience additional timing differences during the correction period
Solution Approach 1:
The patent applies preliminary action by having the primary chip transmit its timer value to secondary chips before making any corrections. This ensures that secondary chips have the most current reference value before the primary timer is adjusted, preventing timing inconsistencies during the correction process.
Solution Approach 2:
The system uses periodic transmission of timer values from the primary to secondary chips, combined with periodic corrections. This periodic action ensures that synchronization information is refreshed regularly, maintaining both stability and consistency across all chips even as corrections are made.
Data Source
AI summary
A new approach is proposed that supports timer synchronization among multiple chips. Under the multi-chip configuration, a secondary timer circuitry of a secondary chip is to be synchronized with a primary timer circuitry of a primary chip. A first secondary timer value is sampled at the secondary timer circuitry as triggered by a first sampling trigger signal when the primary timer circuitry reaches a first primary timer value. A second primary timer value is then sampled at the primary timer circuitry as triggered by a second sampling trigger signal when the secondary timer circuitry reaches a second secondary timer value. A timer correction value is calculated based on the differences between the first primary and secondary timer values and the second primary and secondary timer values. The timer correction value is applied to the secondary timer circuitry to synchronize the primary timer circuitry with the secondary timer circuitry.