Multichip Interconnect Underfill for Stress-Resistant Fine Jet Packaging
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Solution Overview
Problem
Existing technologies fail to effectively address the structural integrity and reliability issues in multi-chip packaging, particularly due to thermo-mechanical deformations and thermal stress between chips and the mechanical stress between chips and interconnect structures, leading to micro-joint fractures and contamination during soldering processes.
Innovation Solution
An underfill layer is formed between chips and interconnect structures, and between chips, using a capillary action to form a mechanical bond between chips and chips, using a mechanical bond between chips and chips, using a mechanical stress, and between chips themselves, reducing the stress and contamination during soldering processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If underfill layer is formed using capillary action to bond chips, then structural integrity and reliability are improved, but manufacturing complexity increases
Solution Approach 1:
The underfill layer acts as an intermediary material between the chips and interconnect structures, providing mechanical bonding and stress relief. The layer is formed through capillary action, where the underfill material automatically flows into the gaps between components without requiring complex external application equipment, thus improving reliability while controlling manufacturing complexity
Solution Approach 2:
The patent replaces traditional mechanical bonding methods with capillary action-driven underfill formation. Instead of using mechanical pressure or adhesive application systems, the underfill material self-assembles through capillary forces, simplifying the manufacturing process while achieving reliable mechanical bonds between chips and interconnect structures
2Reliability
If underfill layer is formed to reduce thermal stress, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes capillary action to form the underfill layer, which naturally adapts to varying gap dimensions between chips and interconnect structures. By changing the physical mechanism from precision-controlled adhesive application to capillary-driven self-leveling, the system tolerates greater variations in gap spacing while still achieving uniform stress distribution and reliable bonding
Solution Approach 2:
The underfill material performs self-alignment and self-leveling through capillary action, automatically filling gaps to the appropriate level without requiring precise external control. This self-service mechanism reduces the manufacturing precision requirements for gap control while ensuring uniform stress relief across the package structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The underfill layer reduces micro-joint fractures and contamination, allowing for faster attachment to organic substrates without pre-cooling, enhancing structural integrity and reliability.
Implementation Method 1
An underfill layer is formed between chips and interconnect structures, and between chips, using a capillary action to form a mechanical bond
Data Source
AI summary
An interconnected semicondcutor subassembly structure and formation thereof. The interconnected semicondcutor subassembly structure includes an interconnect structure, and first and second semicondcutor dies bonded to respective portions of a top surface of the interconnect structure. The interconnected semicondcutor subassembly structure further includes an underfill layer formed within a first gap located between a bottom surface of the first semiconductor die and the first portion the top surface of the interconnect structure, formed within a second gap located between the bottom surface of the second semiconductor die and the second portion of the top surface of the interconnect structure, and formed within a first portion of a third gap located between the first semicondcutor die and the second semicondcutor die. A top surface of the underfill layer formed within the first portion of the third gap located between the first and second semicondcutor dies has a concave meniscus shape.