Multi-Clock Domain DFT Testing with Shared Capture Clock
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Solution Overview
Problem
Design for Test (DFT) techniques face challenges when testing data paths that span multiple clock domains, as prior attempts to use a common capture clock signal often result in hold time errors due to the complexity of controlling data propagation across separately clocked components.
Innovation Solution
Implementing a method and circuit that generate a shared capture clock signal, which is selectively applied to only the domain of interest during appropriate times, eliminating hold time errors by disabling the clock signal in other domains, and using logic to control the clock selection and data propagation across multiple clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a common capture clock signal is applied across multiple clock domains, then DFT testing can be performed across domains, but hold time errors occur because data propagation time exceeds capture time
Solution Approach 1:
The patent segments the multi-domain testing problem by sequentially selecting individual domains to receive the common capture clock signal. Instead of applying the clock to all domains simultaneously, the controller enables the clock for one domain at a time based on which domain currently holds the data of interest, thereby preventing hold time violations while maintaining cross-domain testing capability
Solution Approach 2:
The patent implements dynamic clock signal distribution by using a controller to selectively enable and disable the common capture clock signal for different domains based on real-time data location. The clock assignment changes dynamically during the testing sequence, allowing the system to adapt to the current state of data propagation across domains
2Reliability
If separate clock signals are used for each domain, then data propagation timing is controlled, but controlling the entire data path becomes difficult
Solution Approach 1:
The patent employs a single common capture clock signal that serves multiple domains sequentially, replacing the need for separate clock control for each domain during testing. This universal clock approach simplifies the control architecture while maintaining the ability to test data paths across all domains by timing the clock enablement to match data arrival at each domain
Data Source
AI summary
Methods, circuits and systems are provided to test data paths that traverse multiple clock domains using a common capture clock that is applied to multiple domains. Test data is launched to a first clock domain, and each of the clock domains is selected to receive the common capture clock signal while the test data propagates through the selected clock domain. The test data is capture after it has propagated through each of the multiple domains in response to the shared domains. Applying a common capture clock to each of the different domains eliminates hold time errors that might otherwise occur as the data transitions from one clock domain to another.