Multi-Clock Memory Command Protocol for High-Density Addressing
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Solution Overview
Problem
Existing memory devices face challenges in efficiently accessing memory cells with high density and reduced operational latency while minimizing the number of command/address (CA) bus pins and die size, particularly in emerging technologies that require flexible page sizes and increased activation power.
Innovation Solution
Implementing a multi-clock cycle memory command protocol that allows access commands to be transmitted over multiple clock cycles, using a hybrid gap controlled approach to insert gaps between clock cycles, enabling efficient decoding and access instructions without increasing the number of command/address pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more address bits are transmitted to support high density memory, then memory capacity increases, but the number of command/address pins and die size increase
Solution Approach 1:
The patent segments the address transmission into multiple clock cycles. Instead of transmitting all address bits simultaneously requiring more pins, the address is divided and transmitted sequentially across multiple clock edges (rising and falling edges) using the existing pin infrastructure, thereby supporting high density without increasing pin count or die size.
Solution Approach 2:
The patent adds the time dimension to address transmission by utilizing multiple clock cycles. The address bits are transmitted across different time intervals (multiple clock edges) rather than all at once, effectively using the time dimension to accommodate more address bits without requiring additional spatial resources like pins or die area.
2Quantity of substance
If more address bits are transmitted to support high density memory, then memory capacity increases, but the number of command/address pins increases
Solution Approach 1:
The address transmission is segmented across multiple clock cycles, allowing the existing command/address pins to handle more address bits by transmitting them sequentially rather than requiring additional pins for parallel transmission.
Solution Approach 2:
The solution transitions from spatial expansion (adding more pins) to temporal expansion (using multiple clock cycles), thereby accommodating more address bits for high density memory without increasing the number of command/address pins.
3Productivity
If traditional single-clock cycle command protocol is used, then device complexity is low, but operational latency increases and memory access efficiency decreases
Solution Approach 1:
The patent employs periodic action by utilizing both rising and falling edges of clock cycles for address transmission. This periodic utilization of clock edges enables more efficient memory access by transmitting address bits across multiple periodic clock cycles, improving productivity while managing protocol complexity through structured periodic communication.
Solution Approach 2:
The command protocol maintains continuous useful action by utilizing every clock edge (both rising and falling) for address transmission. This continuous utilization of clock cycles improves memory access efficiency and reduces operational latency compared to idle clock cycles in traditional protocols.
4Use of energy by moving object
If page size is decreased to reduce activation power, then power consumption decreases, but the number of row address terms increases
Solution Approach 1:
The patent uses the time dimension (multiple clock cycles) to transmit the increased number of row address terms required when page size is decreased. This allows smaller page sizes with more address terms to be supported without increasing pin count, as the additional address information is transmitted sequentially across multiple clock edges.
Solution Approach 2:
The increased row address terms resulting from smaller page sizes are segmented and transmitted across multiple clock cycles. This segmentation allows the system to handle more address terms efficiently using existing pin infrastructure, enabling reduced page sizes for lower activation power.
Data Source
AI summary
Systems and methods for providing memory access commands to memory circuitry using a gap controlled multi-clock cycle memory command protocol is described. More than one memory commands are combined into one multi-clock cycle memory command using gap controlled multi-clock cycle memory command protocol. The number of clock cycles included in the gap between two clock cycles in the multi-clock cycle memory command is controlled and adjustable.