Multi-Clock Phase Locking via Downsampling for Servo Writing
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Solution Overview
Problem
Existing data storage systems face challenges in synchronizing multiple clock signals of different frequencies, which is crucial for precise data access and self-servo writing operations in hard disc drives, but current methods are inefficient and require expensive equipment for writing servo patterns.
Innovation Solution
A clock synchronization module that includes digital divider circuits and a phase lock loop to downsample and synchronize clock signals of different frequencies, allowing for precise alignment and synchronization of read and write clocks, enabling efficient self-servo writing and data access operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple clock signals of different frequencies are used for read and write operations, then data access efficiency is improved, but clock synchronization difficulty increases
Solution Approach 1:
A phase lock loop circuit is introduced as an intermediary mechanism to synchronize the phases of multiple clock signals with different frequencies. The PLL compares the phases of reference and input clock signals, generates a phase error signal, and adjusts the input clock phase accordingly, enabling precise synchronization without requiring complex external equipment.
Solution Approach 2:
The system employs feedback control through the phase lock loop, where the phase error between clock signals is continuously detected and fed back to adjust the clock phase. This closed-loop feedback mechanism automatically maintains synchronization, reducing the need for expensive external synchronization equipment and simplifying the overall system.
2Manufacturing precision
If expensive equipment is used for writing servo patterns, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The system uses self-servo writing capability where the hard disc drive writes its own servo patterns using internally generated clock signals synchronized through the phase lock loop. This eliminates the need for expensive external servo writing equipment, reducing manufacturing costs while maintaining precision through the feedback-controlled clock synchronization.
Solution Approach 2:
The patent replaces mechanical/electronic servo writing equipment with a software-controlled phase lock loop system that uses digital signal processing to synchronize clocks. This substitution of complex hardware with a control algorithm-based system reduces equipment costs while maintaining or improving synchronization precision.
3Device complexity
If clock synchronization is performed without downsampling, then device complexity is reduced, but synchronization precision deteriorates
Solution Approach 1:
The clock signals are processed through digital divider circuits that downsample the high-frequency clock signals to lower frequencies before phase comparison. This segmentation of the frequency range allows the phase lock loop to operate more effectively with improved phase detection precision, while the digital dividers provide a systematic way to handle different frequency domains.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables accurate and efficient synchronization of multiple clock signals, reducing the need for expensive equipment and improving manufacturing throughput by allowing for simultaneous or staggered writing of servo patterns across multiple disc surfaces, thereby enhancing data storage precision and speed.
Implementation Method 1
The phase lock loop may be configured to synchronize phases of the first downsampled clock signal and the second downsampled clock signal by adjusting a phase of the second clock signal via the second clock circuit based on a phase error between the first downsampled clock signal and the second downsampled clock signal
Data Source
AI summary
Systems and methods are disclosed for phase locking multiple clocks of different frequencies. In certain embodiments, an apparatus may be configured to downsample a first clock having a first frequency and a second clock having a second frequency into downsampled clocks having the same frequency. The apparatus may adjust a frequency of the second clock so that the downsampled clocks are phase aligned. The apparatus may reset counters of the divider circuits that perform the downsampling so align them to a counter for the first clock. A counter for the second clock may also be reset to align with the counter for the first clock. The synchronized clocks may be applied in data storage operations, such as self-servo writing operations, where the first clock may be a read clock and the second clock may be a write clock.