Multi-Clock Signal Transmission Between Serial Circuit Modules
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Solution Overview
Problem
Large-scale digital circuits face inefficiencies in signal transmission due to cumbersome and time-consuming processes, particularly in complex calculations or analog simulations, where data volume is large and processing time is prolonged.
Innovation Solution
The method involves dividing a digital circuit into multiple circuit modules connected in series, with high-speed data transmission between adjacent modules using a second clock signal, allowing signal transmission to be completed within one low-speed clock cycle, thereby optimizing operation processing and signal transmission without additional clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large-scale digital circuit performs complex calculation or analog simulation with large data volume, then the circuit can achieve complex function processing, but the processing becomes cumbersome and takes a very long time
Solution Approach 1:
The patent divides the large-scale digital circuit into multiple circuit modules connected in series, where each module performs specific operation processing. This segmentation allows parallel processing of different data portions across modules, significantly reducing overall processing time while maintaining complex function capabilities. The circuit is partitioned into functional units that can operate simultaneously on different segments of the input data.
2Productivity
If the circuit is divided into multiple circuit modules connected in series, then the circuit can be optimized for operation processing, but the signal transmission between modules becomes cumbersome and time-consuming
Solution Approach 1:
The patent introduces a high-speed data transmission module as an intermediary between circuit modules. This dedicated transmission module handles all signal exchanges between adjacent circuit modules, providing a specialized high-speed communication channel that eliminates the time penalty of inter-module signaling. The intermediary transmission module acts as a buffer and accelerator for data flow between processing units.
3Speed
If high-speed data transmission is used between adjacent circuit modules, then signal transmission can be completed within one low-speed clock cycle, but additional clock cycles are required for transmission
Solution Approach 1:
The patent employs periodic high-speed data transmission synchronized with the low-speed clock cycles. The high-speed transmission occurs in periodic bursts during each low-speed clock cycle, allowing complete data transfer between adjacent modules within a single low-speed cycle. This periodic synchronization ensures that transmission completes before the next processing cycle begins, eliminating the need for additional clock cycles.
Data Source
AI summary
The present disclosure provides a signal transmission method and a signal transmission device, which are applied to a digital circuit including a plurality of circuit modules connected in series, and each circuit module is configured to perform corresponding operation processing based on a first clock signal provided by a first clock. The method includes: under driving of a second clock signal provided by a second clock, transmitting a first signal output by a current circuit module to a target circuit module in response to reception of the first signal, the first signal is a signal output by the current circuit module when operating based on the first clock signal, transmission of the first signal is completed within a current clock cycle of the first clock, and a clock rate of the second clock is greater than that of the first clock.