Multicore Avionic Processor Deterministic Execution via Private Memory Slots
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Solution Overview
Problem
Multicore avionic systems face challenges in achieving deterministic execution cycles due to unpredictable access times and inefficiencies in memory usage, particularly in time-critical applications, leading to increased risk of breakdowns and underutilization of processing power.
Innovation Solution
A method for loading and executing instructions in a multicore avionic system using private memory and memory controllers, where cores access memory in predetermined slots to minimize shared memory access and latency, allowing for deterministic execution cycles and efficient use of multi-core processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multicore processors with shared memory are used to improve processing power, then productivity increases, but execution time becomes unpredictable due to shared memory access latency
Solution Approach 1:
The patent divides the memory system into private memory regions associated with each processor core. Each core has dedicated cache memory and private memory space, eliminating the need to access shared memory for routine operations. This segmentation allows each core to operate independently with deterministic execution times while maintaining high processing power through parallel operations across multiple cores.
2Speed
If private memory is used for each core to reduce latency, then execution speed improves, but device complexity increases
Solution Approach 1:
The patent combines private memory resources across multiple cores to form a unified memory system that appears as shared memory to software but operates as private memory at the hardware level. This merging approach maintains the speed benefits of private memory while simplifying the software interface and reducing overall system complexity through standardized memory management.
Solution Approach 2:
The memory controller is designed to universally manage both private memory allocations for each core and coordinated access patterns when inter-core communication is needed. This multi-functional memory controller handles cache management, memory allocation, and synchronization operations, reducing the need for separate specialized hardware components.
3Adaptability or versatility
If shared memory access is allowed for inter-core communication, then adaptability improves, but access time becomes unpredictable
Solution Approach 1:
The patent introduces a memory controller as an intermediary between cores and memory resources. This controller manages all memory access requests, coordinating transfers between private memory spaces and handling cache coherence. By acting as a mediator, it enables flexible inter-core communication while maintaining deterministic timing through centralized control and scheduling of memory operations.
Data Source
AI summary
A method and device for loading and executing a plurality of instructions in an avionics system including a processor including at least two cores and a memory controller, each of the cores including a private memory. The plurality of instructions is loaded and executed by execution slots such that, during a first execution slot, a first core has access to the memory controller for transmitting at least one piece of data stored in the private memory thereof and for receiving and storing at least one datum and an instruction from the plurality of instructions in the private memory thereof, while the second core does not have access to the memory controller and executes at least one instruction previously stored in the private memory thereof and such that, during a second execution slot, the roles of the two cores are reversed.