Multicore Processor Parallel Boot Time Reduction
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Solution Overview
Problem
Existing methods for booting processor and programmable logic device environments are inefficient, particularly in automotive systems where rapid initialization is required, often exceeding the three hundred millisecond limit due to sequential initialization processes and limited memory capacity in EEPROMs.
Innovation Solution
Implementing a multicore processor where one core remains active to parallelize initialization tasks with the bootstrap processor, allowing simultaneous silicon and platform initialization, and using a flash-based Field Programmable Gate Array (FPGA) to reduce boot time by initializing the programmable logic device in parallel with the bootstrap processor's operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If sequential initialization processes are used to boot the processor and programmable logic device, then system stability is maintained, but boot time exceeds the three hundred millisecond limit
Solution Approach 1:
The patent applies preliminary action by pre-configuring the programmable logic device using a flash-based configuration storage that retains configuration data without power. This allows the device to skip lengthy configuration loading during boot, enabling parallel initialization with the processor and achieving boot times within the 300ms limit while maintaining system stability.
Solution Approach 2:
The patent transitions from sequential to parallel initialization by introducing a second dimension of operation. The processor and programmable logic device initialize simultaneously rather than one after the other, fundamentally changing the temporal dimension of the boot process. This parallel execution architecture reduces boot time without compromising system stability through coordinated initialization protocols.
2Loss of time
If EEPROM memory is used for configuration storage, then system reliability is maintained, but memory capacity limitations prevent rapid boot
Solution Approach 1:
The patent applies parameter changes by switching from EEPROM to flash-based configuration storage. This changes the physical and operational parameters of the memory system, providing both larger capacity and faster read speeds. The flash memory can store complete device configurations and load them rapidly during boot, eliminating the capacity and speed limitations of EEPROM while maintaining configuration reliability.
3Loss of time
If all processor cores are initialized sequentially by the bootstrap processor, then initialization completeness is ensured, but boot time increases beyond automotive requirements
Solution Approach 1:
The patent applies segmentation by dividing the initialization responsibilities between the bootstrap processor and application processor cores. Different initialization tasks are segmented and assigned to different processors, allowing simultaneous execution. The bootstrap processor handles system-level initialization while application processor cores initialize in parallel, ensuring all necessary components are initialized without sequential delays.
Solution Approach 2:
The patent introduces an intermediary mechanism through the flash-based configuration storage that mediates between the processor and programmable logic device. This intermediary provides shared configuration data that both processors can access simultaneously, coordinating their parallel initialization efforts and ensuring completeness without requiring one processor to wait for the other.
Data Source
AI summary
Methods and apparatus for boot time reduction in a processor and programmable logic device environment are disclosed. An example apparatus includes a multicore processor including a first core and a second core. A bootstrap processor is to initialize the first core into a standby mode and initialize the second core into a non-standby mode. A programmable logic device is to be programmed with instructions to be executed by the programmable logic device by the second core via a first connection initialized by the second core. The bootstrap processor is to, upon completion of the programming of the programmable logic device, initialize a data connection between the programmable logic device and the second core.