Multicore Bus Architecture Wire Reduction via Shared Channels
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Solution Overview
Problem
Traditional bus protocols in digital data processing suffer from performance losses due to the need for a two-way communication handshake, which leads to increased latency and wire congestion, especially as address and data widths increase, resulting in reduced communication performance and longer design schedules.
Innovation Solution
The Multicore Bus Architecture (MBA) protocol shares a single physical channel for all transaction types, using a Transaction Attribute Channel (TAC) and a Transaction Data Channel (TDC) to transmit attributes and data, eliminating the need for separate channels and reducing the number of required wires, and employs a credit-based system to manage transactions, allowing for higher throughput and reduced latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional bus protocols use separate physical channels for read, write, and coherence transactions, then transaction types can be transmitted independently, but the number of physical wires increases significantly causing wire congestion and increased area
Solution Approach 1:
The patent merges multiple separate physical channels (read, write, coherence) into a single shared physical bus. All transaction types share the same data and address channels, significantly reducing the number of wires required while maintaining the ability to handle different transaction types through protocol-level multiplexing
Solution Approach 2:
The shared bus channels are designed to be universal, handling multiple transaction types (read, write, coherence) through a single infrastructure. The same physical wires carry different types of transactions by using transaction type identification and appropriate protocol handling at the controller level
2Reliability
If traditional bus protocols use two-way communication with request and acknowledge signals, then transaction reliability is improved, but transaction latency increases due to handshake cycles
Solution Approach 1:
The patent implements a credit-based system where credits are pre-allocated to masters before transactions occur. This preliminary allocation of resources allows masters to immediately initiate transactions without waiting for handshakes, reducing latency while maintaining reliability through the credit accounting mechanism that ensures slaves are ready to receive transactions
3Reliability
If transactions wait for acknowledge signals in traditional bus protocols, then data integrity is ensured, but bus utilization decreases as other transactions are blocked
Solution Approach 1:
The patent enables continuous bus operation by allowing multiple transactions to be in flight simultaneously through the credit-based system. Masters can continuously issue transactions as long as they have credits, and slaves process transactions asynchronously, eliminating idle wait cycles and maximizing bus utilization while maintaining data integrity through credit tracking
Data Source
AI summary
The Multicore Bus Architecture (MBA) protocol includes a novel technique of sharing the same physical channel for all transaction types. Two channels, the Transaction Attribute Channel (TAC) and the Transaction Data Channel (TDC) are used. The attribute channel transmits bus transaction attribute information optionally including a transaction type signal, a transaction ID, a valid signal, a bus agent ID signal, an address signal, a transaction size signal, a credit spend signal and a credit return signal. The data channel connected a data subset of the signal lines of the bus separate from the attribute subset of signal lines the bus. The data channel optionally transmits a data valid signal, a transaction ID signal, a bus agent ID signal and a last data signal to mark the last data of a current bus transaction.