Multi-Core Processor Cache Scheduling for Deterministic Resource Access

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Solution Overview

Problem

Multi-core processors experience interference and uncertainty in data processing time due to concurrent execution of software applications, leading to delays and performance degradation, especially in embedded systems requiring deterministic processing.

Innovation Solution

Implementing a control method for multi-core processors with private cache memory and a software access controller to anticipate and schedule transactions with common resources during dedicated time windows, ensuring temporal isolation and reducing wait times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple software applications are executed concurrently on multiple cores, then overall processing throughput is improved, but data processing time becomes uncertain and interference occurs

Engineering Contradiction:
Improveprocessing throughputVSAvoiddata processing time uncertainty
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments the execution of software applications by dividing them into periodic tasks with acquisition, execution, and restitution phases. Each periodic task is assigned to a dedicated core and executed in distinct time phases, preventing overlap and interference between concurrent applications while maintaining high throughput

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by pre-scheduling periodic tasks and preparing their execution phases in advance. The acquisition phase collects data beforehand, and the restitution phase prepares results before they are needed, reducing waiting time and ensuring deterministic processing

Inventive Principle:
Principle #10Preliminary action

2Reliability

If periodic tasks are executed on dedicated cores with predetermined schedules, then determinism in processing time is improved, but system complexity increases

Engineering Contradiction:
Improvedeterminism in processing timeVSAvoidtask execution model complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by dedicating specific cores to specific periodic tasks with predetermined schedules. Each core has a specialized role executing tasks in specific phases (acquisition, execution, restitution), ensuring determinism for time-critical operations while keeping the complexity localized to individual cores rather than the entire system

Inventive Principle:
Principle #3Local quality

3Reliability

If transactions to common resources are processed sequentially, then resource conflicts are resolved, but execution delays occur

Engineering Contradiction:
Improveresource conflict resolutionVSAvoidapplication execution speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements periodic action by organizing access to common resources into periodic tasks with predetermined schedules. Each task has designated acquisition and restitution phases that occur periodically, allowing multiple tasks to share resources in a structured, conflict-free manner while maintaining high execution speed through parallel processing of non-conflicting operations

Inventive Principle:
Principle #19Periodic action

Data Source

PatentEP3559810B1Method for controlling a multi-core processor and associated computer
Publication Date: 2026.02.18 THALES SA
  • EP3559810B1 patent drawingFigure 1
  • EP3559810B1 patent drawingFigure 2~4

AI summary

The invention relates to a control method for a multi-core processor comprising a plurality of cores (10) sharing at least one common material resource (12) according to a sharing policy based on different time windows (F), each time window (F) being attributed to at least one core (10). The control method comprises the anticipation of a request to be emitted by a software application (AP) run by a core (10) and requiring a transaction between said core (10) and the common resource (12), the planning of the transaction in a time window (F) to be attributed to said core (10) for access to the common resource (12), the implementation of the planned transaction and the loading of the data into a private cache memory (16) of said core (10), and the restitution of the data to the software application (AP) from the private cache memory (16).