Multicore Cache Architecture for Deterministic Memory Access
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Solution Overview
Problem
Existing multicore processor systems face challenges in ensuring deterministic data processing, particularly in safety-critical applications like aviation, due to unpredictable memory access and resource contention, leading to conservative execution time estimates and inefficient resource utilization.
Innovation Solution
A multicore processor system with intermediate storage units assigned to each processor unit, which pre-store information elements for deterministic data processing, reducing resource contention and enabling static time analysis, and incorporating a state and control logic to manage memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If arbitration logic is used to determine exclusive access to shared resources, then resource access control is improved, but program execution of other requestors is blocked
Solution Approach 1:
The patent segments the memory system into private L2 cache memory associated with each processing core and a shared L3 cache memory. This segmentation allows each core to have dedicated fast access to its own data while sharing less frequently accessed data through the L3 cache, reducing arbitration contention and improving parallel execution throughput.
Solution Approach 2:
The patent introduces an intermediary memory hierarchy (L2 and L3 caches) between the processing cores and main memory. This intermediary structure provides deterministic access times for time-critical operations by keeping frequently accessed data in the cache hierarchy, reducing the need for arbitration when accessing shared resources.
2Reliability
If conservative upper execution time limits are used for high-integrity applications, then reliability is improved, but available processing resources cannot be fully utilized
Solution Approach 1:
The patent segments applications into time-critical and non-time-critical categories, and similarly segments the memory hierarchy into private L2 cache and shared L3 cache. Time-critical applications access data through the private L2 cache with deterministic access times, while non-time-critical applications can utilize the shared L3 cache and main memory, allowing conservative timing guarantees only where necessary and maximizing overall resource utilization.
Solution Approach 2:
The patent applies different quality characteristics to different parts of the memory system: the private L2 cache provides deterministic, low-latency access for time-critical operations, while the shared L3 cache provides higher capacity with less stringent timing requirements. This local differentiation allows tight execution time limits only for time-critical code paths while allowing more flexible resource sharing for non-critical operations.
3Productivity
If high-integrity and low-integrity applications run on the same processor, then resource utilization is improved, but execution time limits become more conservative
Solution Approach 1:
The patent segments the memory access paths by introducing private L2 cache memory for each processing core. High-integrity applications running on a core can access their frequently used data through the private L2 cache with deterministic timing, isolated from memory access patterns of low-integrity applications. This segmentation allows mixed-integrity workloads to coexist on the same processor while maintaining tight execution time limits for high-integrity code.
4Power
If the number of cores per processor is increased, then processing power is improved, but execution time estimates become more conservative
Solution Approach 1:
The patent segments the cache hierarchy into private L2 cache for each core and shared L3 cache. This segmentation ensures that each core has dedicated fast memory for its time-critical operations, isolating the deterministic timing behavior from the effects of having multiple cores. As a result, increasing the number of cores increases processing power without forcing more conservative execution time estimates, since each core's critical path timing remains independent.
Data Source
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AI summary
The present invention relates to a multicore processor system (1) for deterministic data processing in a data processing unit. Such a system (1) comprises a data processing unit (2) having at least two processor units (3), a common interface unit (5), which is designed to couple the at least two processor units (3) to at least one shared main memory unit of the data processing unit (2) and at least one common further resource (6) of the data processing unit (2). Each processor unit (3) further comprises a respective intermediate storage unit (4) which is coupled to this processor unit (3) and is arranged between the respective processor unit (3) and the common interface unit (5) so that at least one information element for deterministic data processing in the respective processor unit (3) is storable in the intermediate storage unit (4) prior to this deterministic data processing. A method M for deterministic data processing in a data processing unit (2) is further disclosed.