Multicore Cache Invalidation Consolidation for Lower Processing Latency
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Solution Overview
Problem
In multicore processor systems with shared memory banks, simultaneous access by multiple cores leads to multiple invalidation commands, causing latency due to the processing of these commands by cache controllers, which existing techniques struggle to handle efficiently.
Innovation Solution
A directory-based cache coherence protocol that consolidates multiple invalidation commands into a single command format, allowing simultaneous processing by the cache controller, using precise, array-of-slots, and mask-of-sets commands based on set indices and way information, and bit masks to manage cache line invalidations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple invalidation commands are sent simultaneously to cores from different memory banks, then cache coherence is maintained across all banks, but processing latency increases because the cache controller must handle multiple commands sequentially
Solution Approach 1:
The patent merges multiple invalidation commands into a single consolidated command that contains information about multiple cache lines to be invalidated. The cache controller receives this single consolidated command and processes all invalidations simultaneously, eliminating the sequential processing delay while maintaining cache coherence across all memory banks.
Solution Approach 2:
The patent introduces an intermediary consolidation structure that collects invalidation requests from multiple memory banks and transforms them into a unified command format. This intermediary layer absorbs the complexity of handling multiple simultaneous commands, allowing the cache controller to process invalidations in parallel without requiring changes to its core architecture.
2Productivity
If the cache controller processes multiple invalidation commands simultaneously, then processing latency is reduced, but the complexity of the cache controller increases
Solution Approach 1:
The patent segments the invalidation information into distinct fields within a consolidated command structure. Each invalidation request is represented as a separate element with specific attributes (cache line address, valid bit, etc.), allowing the cache controller to process multiple invalidations systematically through structured data handling rather than complex control logic.
Solution Approach 2:
The patent changes the parameter representation of invalidation commands by encoding multiple invalidation requests into a single command with extended parameters. Instead of using multiple separate commands with simple parameters, the system uses one command with compound parameters that can represent multiple cache lines, reducing the number of control signals required.
3Productivity
If precise invalidation of individual cache lines is performed, then cache performance is optimized by keeping valid lines, but the complexity of tracking and processing individual cache line invalidations increases
Solution Approach 1:
The patent creates a consolidated copy of invalidation information that represents multiple cache line invalidations in a single data structure. This consolidated command serves as a copy of the essential invalidation information from multiple sources, allowing the cache controller to process all invalidations without maintaining separate tracking state for each individual invalidation request.
Data Source
AI summary
A processor comprising multiple cores, each including a local cache; multiple memory banks forming a shared memory for the multiple cores; a directory-based cache coherence protocol manager, comprising for each core a circuit for consolidating multiple cache line invalidation commands received from the different memory banks. The consolidation circuit comprises a counter for counting the received invalidation commands; and a selection circuit configured to, depending on whether the count of received invalidation commands is equal to 1 or greater, transmit to the cache the single received invalidation command or a consolidated invalidation command for the cache lines identified in the received invalidation commands, in a format usable by the cache to simultaneously invalidate the identified cache lines.