Multicore Performance Simulation via Cache Synchronization
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Solution Overview
Problem
Conventional techniques for calculating performance values of programs on multicore processors with shared cache memory suffer from reduced accuracy due to varying results from cache hits and misses based on the order of core access, especially when multiple cores access the same or close destinations.
Innovation Solution
A calculating device and method that executes simulations for each core, synchronizes these simulations, and corrects performance values by simulating cache operations after synchronization, ensuring accurate calculation of cache hits and misses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If performance values are calculated for each core independently without synchronization, then calculation speed is improved, but accuracy of performance value calculation deteriorates due to incorrect cache hit/miss prediction
Solution Approach 1:
The patent performs preliminary actions by executing simulations for each core independently to obtain initial performance values and access instruction sequences. These preliminary simulation results are then used to determine the order of access instructions, which is subsequently used to synchronize the simulations and calculate accurate cache hit/miss predictions. This preliminary independent calculation enables later accurate synchronization without requiring complete dependency resolution beforehand.
Solution Approach 2:
The patent implements feedback by using the results of independent core simulations to determine the order of access instructions, which then feeds back into the synchronization process. The performance values and access patterns obtained from initial simulations are fed back to establish the correct execution order, allowing accurate cache simulation afterward. This feedback loop ensures that the synchronization uses actual observed behavior rather than assumptions.
2Loss of time
If cache memory operation is simulated for each core independently, then simulation time is reduced, but correctness of cache hit/miss determination deteriorates
Solution Approach 1:
The patent segments the simulation process into two distinct phases: first, independent simulations for each core to obtain performance values and access instruction sequences; second, synchronized simulation of cache memory operations using the determined order of access instructions. This segmentation allows the first phase to run quickly without correctness constraints, while the second phase ensures correctness by using the order information from the first phase. The segmentation resolves the contradiction by separating speed-oriented and correctness-oriented operations.
Solution Approach 2:
The patent performs preliminary simulation of each core's execution to determine the order of access instructions before performing the cache memory operation simulation. This preliminary action captures the execution sequence without immediately simulating cache effects, allowing fast independent simulation followed by accurate synchronized cache simulation. The preliminary determination of access order enables correct cache simulation without requiring simultaneous execution tracking.
3Productivity
If access instructions from multiple cores are executed in parallel without synchronization, then execution efficiency is improved, but accuracy of performance evaluation deteriorates due to race conditions in shared cache memory
Solution Approach 1:
The patent executes access instructions from multiple cores in parallel during the preliminary simulation phase to determine their execution order. This preliminary parallel execution captures the race condition behavior and determines the correct sequence in which access instructions should be processed. The determined order is then used in the second phase to synchronize cache memory operations, ensuring accurate performance evaluation while maintaining the efficiency of parallel execution in the first phase.
Solution Approach 2:
The patent uses feedback from parallel execution to determine the correct order of access instructions. By observing which core's access instruction executes first in the parallel simulation, the system feeds back this ordering information to the synchronization mechanism. This feedback ensures that the subsequent cache memory simulation respects the actual execution order, resolving the accuracy issue while maintaining parallel execution efficiency in the preliminary phase.
Data Source
AI summary
A calculating device including; a controller configured to execute, for a multicore processor, a first calculation process of calculating a first performance value of a first code executed by the first core and including a first access instruction by executing a first simulation, a second calculation process of calculating a second performance value of a second code executed by the second core and including a second access instruction by executing a second simulation, a synchronization process of synchronizing the first and the second simulations when the first access instruction is executed in the first simulation, and a correction process of correcting the first performance value, by executing a third simulation to simulate an operation of the cache memory when the first core accesses the main memory through the cache memory in accordance with the first access instruction, after the synchronization by the synchronization process.