Multicore Interface Card with CPU Segmentation for Safe Packet Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high costs and time-consuming validation and certification processes for safety-related devices in train communication networks, combined with the need for space-saving designs and flexible interface cards that simplify maintenance, are not adequately addressed by existing technologies.
Innovation Solution
A multicore architecture with a reconfigurable logic device featuring a first CPU for processing safety-related data and a second CPU for non-safety-related data, allowing for firmware updates on the second CPU without reassessment, along with a hardware firewall to prevent interference between the CPUs, and a data splitting device to segregate safety and non-safety data packets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single CPU processes both safety-related and non-safety-related data, then device complexity is reduced, but the risk of data corruption and the need for reassessment after updates increases
Solution Approach 1:
The patent divides the processing system into two separate CPUs: a first CPU dedicated to safety-related data and a second CPU for non-safety-related data. This segmentation isolates safety-critical operations from potential interference, allowing updates to the second CPU without reassessment while maintaining data integrity through physical and logical separation of processing functions.
2Adaptability or versatility
If firmware updates are made to improve functionality, then adaptability is improved, but validation and certification processes increase time and cost
Solution Approach 1:
By segmenting the system into safety-related and non-safety-related processing units, the patent enables independent updates of the second CPU's firmware without triggering reassessment of the entire system. Only the non-safety portion requires validation, significantly reducing certification time and cost while maintaining full adaptability for functionality improvements.
Solution Approach 2:
The patent introduces an intermediary mechanism (the separated CPU architecture with controlled data exchange) that allows firmware updates to occur in the non-safety domain without affecting the safety-certified portion. This intermediary structure acts as a buffer that isolates update operations from the certified safety functions, enabling rapid adaptation without repeated validation.
3Ease of operation
If interface cards provide flexibility for different subsystems, then ease of operation is improved, but device complexity and space requirements increase
Solution Approach 1:
The patent implements a universal interface card design where the second CPU handles multiple non-safety-related functions and protocols through a single integrated unit. This multi-functional approach provides the needed flexibility for different subsystems while avoiding the complexity of multiple specialized interface cards, as the separated architecture allows the non-safety portion to accommodate various protocols without impacting the safety-certified components.
Data Source
Figure 1
Figure 2
Figure 3a~3b
AI summary
The invention relates to a multicore architecture (1) comprising: a reconfigurable logic device (2); the reconfigurable logic device (2) including a first CPU (3) and a second CPU (4); the first CPU (3) being configured to process safety-related data; and the second CPU (4) being configured to process non-safety-related data only. The invention also relates to a corresponding interface card (13) and to a method of processing data packets.