Multi-Core Chip Wiring Layout Without Interconnection Channels
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Solution Overview
Problem
Conventional integrated circuit (IC) chip designs require numerous channels for interconnection lines and buses, leading to increased chip size, signal delays, and inefficiencies due to longer wire lengths and the need for additional clock buffer circuits.
Innovation Solution
Interconnection lines in a system-on-chip are routed directly between partitions without the use of pre-established channels, utilizing transistors within the partitions to provide buffer circuits for signal reinforcement, thereby reducing the need for dedicated channel space and minimizing signal loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pre-established channels are used for interconnection lines, then signal routing is simplified and noise is suppressed, but chip area increases and interconnection lengths become longer
Solution Approach 1:
The patent extracts the interconnection lines from the pre-established channels and routes them directly through the partitions. This removes the unnecessary channel structure while maintaining signal integrity through direct routing, thereby reducing chip area without sacrificing routing reliability.
Solution Approach 2:
The patent changes the routing dimension by allowing interconnection lines to pass through the partition interior rather than being confined to surface-level channels. This dimensional change enables shorter, more direct paths that reduce area usage while maintaining signal quality.
2Ease of manufacture
If pre-established channels are used for interconnection lines, then signal routing is simplified, but interconnection lengths become longer causing signal delays
Solution Approach 1:
The patent segments the chip into partitions with dedicated buffer circuits at their boundaries. This segmentation allows interconnection lines to be routed directly through partition boundaries rather than following lengthy channel paths, reducing interconnection length while maintaining routing simplicity through systematic buffer placement.
Solution Approach 2:
The patent performs preliminary placement of buffer circuits at partition boundaries before final interconnection routing. This preliminary action ensures that signal reinforcement is already in place to handle direct, short-routed interconnections, eliminating the need for long channel-based paths.
3Reliability
If buffer circuits are placed in dedicated channel regions, then signal strength is maintained, but chip area increases
Solution Approach 1:
The patent merges the buffer circuit functionality with the partition boundary structure. Instead of placing buffers in separate channel regions, the buffers are integrated at the partition boundaries where they serve multiple partitions simultaneously, maintaining signal strength while reducing redundant buffer placements and chip area usage.
Solution Approach 2:
The buffer circuits placed at partition boundaries serve multiple functions: they reinforce signals for any interconnection line passing through that boundary, regardless of which specific partitions are connected. This multi-functionality allows a single buffer to serve multiple routing paths, reducing the total number of buffers needed and thereby reducing chip area.
Data Source
AI summary
An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.