Multicore Processor Clock Dividers for Synchronization Power Savings
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Solution Overview
Problem
Current microprocessor architectures face inefficiencies in energy usage during parallel operations due to frequent synchronization events, which require time-consuming operating system calls and voltage adjustments, leading to power wastage and disruptions.
Innovation Solution
A computer architecture that includes a frequency selector for each processor core, allowing for rapid clock frequency adjustments without disrupting communication with other system elements, using a post-divider circuit to reduce clock speed during synchronization events, thereby minimizing power consumption and avoiding the need for multiple voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If processor cores spin to wait for lock availability, then synchronization is achieved, but power consumption increases substantially
Solution Approach 1:
The patent applies dynamics by allowing processor cores to dynamically adjust their operating frequency based on whether they are spinning or executing useful work. Spinning cores operate at a reduced frequency to conserve energy, while cores performing productive tasks maintain full frequency. This dynamic frequency adjustment resolves the contradiction by matching power consumption to actual computational needs during synchronization wait states.
Solution Approach 2:
The patent changes the operating parameter (clock frequency) of processor cores based on their operational state. By reducing the frequency parameter for spinning cores and maintaining higher frequency for productive cores, the system achieves lower overall power consumption while preserving correct synchronization behavior through the frequency selector and post-divider circuitry.
2Use of energy by moving object
If processor cores are suspended and switched to different threads using futex technique, then processor resources are saved, but multiple operating system calls are required which consume many processor cycles
Solution Approach 1:
Instead of suspending and resuming threads through expensive OS calls, the patent keeps threads running but dynamically adjusts the frequency of spinning cores. This allows the thread to remain in a lightweight state without full context switching overhead, resolving the contradiction by avoiding the time-consuming OS call mechanism while still conserving processor resources during wait states.
3Use of energy by moving object
If clock frequency is reduced during spinning, then power consumption decreases, but communication with other system elements may be disrupted
Solution Approach 1:
The patent introduces a frequency selector and post-divider circuit as intermediaries between the reduced-frequency spinning core and the rest of the system. These intermediaries translate the low-frequency signals from the spinning core into compatible signals for other system elements, allowing frequency reduction without disrupting communication integrity.
Solution Approach 2:
The patent segments the clock distribution system by providing separate frequency paths: one path with a post-divider for communication interfaces and another path maintaining full frequency for computational logic. This segmentation allows independent frequency control for different parts of the system, resolving the contradiction between power savings and communication reliability.
Data Source
AI summary
A multicore computer architecture provides for clock dividers on each core, the clock dividers capable of providing rapid changes in the clock frequency of the core. The clock dividers are used to reduce the clock frequency of individual cores spinning while waiting for a synchronization instruction resolution such as a lock variable. Core power demands may be decreased before and after change in dock speed to reduce power bus disruption.