Multi-Core Clock Synchronization via Load-Based Domain Segmentation
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Solution Overview
Problem
In multi-core processor systems, the increasing number of cores leads to unbalanced operation loads, causing significant deviations in system clock ticks across cores, which affects the accuracy and synchronization of upper-layer software timers, making existing synchronization methods inadequate for maintaining reliable and stable operation.
Innovation Solution
The method involves establishing clock synchronization domains, where each core is allocated to a domain, and a core with the lowest load is designated as the master synchronization device. The master domain calculates and adjusts time deviations among slave domains, ensuring synchronization by periodically monitoring and adjusting clock ticks, and switching between master and standby devices as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If each core separately implements clock interrupt function, then system scalability is improved, but clock synchronization accuracy deteriorates due to load unbalance
Solution Approach 1:
The multi-core system is segmented into multiple clock synchronization domains, with each domain containing one or more cores. This segmentation allows independent clock management within each domain while maintaining overall system synchronization, resolving the conflict between scalability and synchronization accuracy.
Solution Approach 2:
A master clock synchronization domain is introduced as an intermediary to coordinate timekeeping across all slave domains. The master domain calculates time deviations and distributes correction values to slave domains, ensuring synchronized clocks throughout the scalable multi-core system without requiring each core to independently maintain perfect synchronization.
2Measurement precision
If timer interrupt interval is set short, then time measurement precision is improved, but system stability deteriorates due to frequent interruptions
Solution Approach 1:
The system uses periodic clock synchronization actions where the master domain periodically detects time deviations and distributes correction values to slave domains. This periodic synchronization mechanism maintains accurate time measurement without requiring continuous high-frequency interrupt handling, thus preserving system stability.
3Productivity
If number of cores increases, then processing capacity is improved, but clock tick synchronization deteriorates due to load unbalance
Solution Approach 1:
Each clock synchronization domain is assigned local quality characteristics where the master domain has authoritative synchronization control while slave domains follow correction instructions. This local quality differentiation allows the system to scale to more cores while maintaining clock tick synchronization through hierarchical domain management rather than requiring uniform core behavior.
Data Source
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AI summary
A time synchronization method and system for a multi-core system are provided, and the time synchronization method comprises the following steps of: A, establishing at least one clock synchronization domain, and respectively allocating each core to each clock synchronization domain; B, selecting a core with a lowest load in each clock synchronization domain as a master clock synchronization source in the clock synchronization domain, and selecting the clock synchronization domain having the master clock synchronization source with a lowest load among various master clock synchronization sources as a master clock synchronization domain, while other clock synchronization domains as slave clock synchronization domains; C, the master clock synchronization domain sending a synchronization deviation detection message to each slave clock synchronization domain, and calculating a time deviation value between each slave clock synchronization domain and the master clock synchronization domain; D, when the time deviation value is greater than a permitted deviation value, the master clock synchronization domain calculating a time adjustment quantity of each slave clock synchronization domain and releasing the time adjustment value to each slave clock synchronization domain, and each slave clock synchronization domain making adjustment based on its time adjustment quantity.