Multicore Coherence Controller With Snoop Filtering for Shared Memory
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Solution Overview
Problem
Multi-core systems face coherency issues due to simultaneous access to shared memory, leading to operational inefficiencies and potential outdated data retrieval, especially when software cache maintenance operations are slow or resource-intensive.
Innovation Solution
A multi-core shared memory controller (MSMC) is implemented with a snoop filter bank, cache tag bank, and memory bank, which includes a coherent slave interface, external memory master interface, and an arbiter circuit to manage memory access requests, determine snoop requests, and allocate virtual channels, ensuring coherent data access and efficient arbitration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software cache maintenance operations are used to manage coherency, then coherency can be maintained, but operational efficiency deteriorates due to slow performance and excessive operational time consumption
Solution Approach 1:
The patent replaces software-based cache maintenance operations with a hardware-based coherency controller that uses snoop filter banks and cache tag banks to automatically detect and manage coherency violations. This hardware mechanism operates in parallel with normal memory access, eliminating the performance penalty of software interventions while maintaining coherency through automatic snoop request generation and tag comparison.
Solution Approach 2:
The snoop filter banks are pre-configured with tag information before coherency violations occur. When a memory access request is made, the controller proactively checks the snoop filter banks and cache tag banks in advance to determine if coherency issues exist, allowing for preemptive handling of coherency violations before they impact system performance.
2Adaptability or versatility
If multiple processing cores access shared memory simultaneously, then system functionality is enhanced, but coherency issues arise leading to outdated data retrieval
Solution Approach 1:
The coherency controller acts as an intermediary between multiple processing cores and shared memory. It intercepts memory access requests, checks the snoop filter banks and cache tag banks to determine if coherency violations exist, and manages the arbitration process. This intermediary mechanism allows multiple cores to access shared memory simultaneously while maintaining data coherency through automated snoop request generation and response handling.
Solution Approach 2:
The system implements feedback through the snoop filter banks that continuously monitor memory access patterns and cache tag states. When a coherency violation is detected, the controller generates appropriate snoop requests and updates the filter banks with new tag information, creating a closed-loop feedback system that automatically maintains coherency across multiple cores without requiring manual intervention.
3Productivity
If a hardware-based coherency controller with snoop filter banks is implemented, then operational efficiency is improved, but device complexity increases
Solution Approach 1:
The coherency controller is segmented into distinct functional units: snoop filter banks for tag storage and monitoring, cache tag banks for coherency state tracking, and arbitration logic for request management. Each segment operates independently but cooperates through standardized interfaces, allowing the complex coherency management function to be distributed across modular components that can be optimized and maintained separately.
Data Source
AI summary
A system includes a multi-core shared memory controller (MSMC). The MSMC includes a snoop filter bank, a cache tag bank, and a memory bank. The cache tag bank is connected to both the snoop filter bank and the memory bank. The MSMC further includes a first coherent slave interface connected to a data path that is connected to the snoop filter bank. The MSMC further includes a second coherent slave interface connected to the data path that is connected to the snoop filter bank. The MSMC further includes an external memory master interface connected to the cache tag bank and the memory bank. The system further includes a first processor package connected to the first coherent slave interface and a second processor package connected to the second coherent slave interface. The system further includes an external memory device connected to the external memory master interface.