Multicore Coherence Controller With Snoop Filtered Shared Memory
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Solution Overview
Problem
Multi-core systems face challenges in maintaining memory coherency efficiently, leading to operational inefficiencies and potential data inconsistencies among processing cores.
Innovation Solution
The implementation of a multi-core shared memory controller (MSMC) with a snoop filter bank, cache tag bank, and memory bank, along with coherent slave interfaces and an external memory master interface, enables effective coherency management by determining snoop requests based on tag states and cache hit statuses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software cache maintenance operations are used to provide coherency, then coherency can be maintained, but operational efficiency deteriorates (slow operations, excessive operational time consumption)
Solution Approach 1:
The patent replaces software-based cache maintenance operations with a hardware-based coherency controller that automatically monitors and manages cache coherency. The coherency controller uses hardware circuits to detect cache hits, generate snoop requests, and invalidate cache lines, substituting the mechanical software execution process with a faster hardware-based mechanism that operates transparently to the processing cores.
Solution Approach 2:
The coherency controller acts as an intermediary between processing cores and memory devices, intercepting memory requests and managing cache coherency without requiring direct software intervention. The controller receives memory requests from cores, checks cache status through snoop filters, and coordinates with memory devices to maintain coherency, thereby eliminating the need for inefficient software cache maintenance operations.
2Adaptability or versatility
If multiple processing cores access the same memory address simultaneously, then system functionality is enhanced, but coherency issues arise (data inconsistencies)
Solution Approach 1:
The coherency controller implements feedback mechanisms where it continuously monitors memory access requests from multiple cores, checks cache status through snoop filters, and sends invalidate signals back to cores or memory devices when coherency violations are detected. This closed-loop feedback system automatically detects and corrects coherency issues arising from simultaneous multi-core access to the same memory addresses.
Solution Approach 2:
The coherency controller serves as a mediator that coordinates access between multiple processing cores and memory devices, ensuring that data inconsistencies are prevented or corrected. When multiple cores access the same memory address, the controller intercepts these requests, checks cache validity, and manages the access sequence to maintain data coherency across all cores.
3Speed
If cached data is modified without committing back to memory, then access speed is improved, but data consistency deteriorates (out of date data in other cores)
Solution Approach 1:
The patent replaces manual cache flush operations with automatic hardware-based coherency management. The coherency controller continuously monitors cache modifications through snoop filters and automatically invalidates or updates cache lines in other cores when modifications are detected, eliminating the need for software-initiated cache maintenance while maintaining data consistency.
Solution Approach 2:
The system implements feedback through the coherency controller that detects when cached data is modified and automatically propagates these changes or invalidations to other cores. The controller monitors write operations, checks cache status, and sends appropriate signals to maintain consistency, allowing fast cached access while preventing data inconsistency.
Data Source
AI summary
A system includes a multi-core shared memory controller (MSMC). The MSMC includes a snoop filter bank, a cache tag bank, and a memory bank. The cache tag bank is connected to both the snoop filter bank and the memory bank. The MSMC further includes a first coherent slave interface connected to a data path that is connected to the snoop filter bank. The MSMC further includes a second coherent slave interface connected to the data path that is connected to the snoop filter bank. The MSMC further includes an external memory master interface connected to the cache tag bank and the memory bank. The system further includes a first processor package connected to the first coherent slave interface and a second processor package connected to the second coherent slave interface. The system further includes an external memory device connected to the external memory master interface.