Multi-Core CPU Core Assignment for Real-Time Processing

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Solution Overview

Problem

Conventional image forming apparatuses face inefficiencies and increased costs due to delayed processing and communication requirements when handling small-sized jobs and parallel processing, particularly with single-core CPUs, which affect responsiveness and scheduling.

Innovation Solution

The implementation of a multi-core CPU architecture where real-time processing necessary tasks are assigned to one core and real-time processing unnecessary tasks to another, optimizing core utilization and reducing scheduling delays and costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single core CPU is used to control both real-time and non-real-time processes, then device complexity is reduced, but processing speed and responsiveness deteriorate due to scheduling delays

Engineering Contradiction:
ImproveCPU architectureVSAvoidprocessing speed
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent divides the CPU into multiple cores, separating real-time processing tasks from non-real-time processing tasks. This segmentation allows each core to handle specific types of processes independently, eliminating scheduling delays and improving overall processing speed while maintaining manageable system complexity.

Inventive Principle:
Principle #1Segmentation

2Productivity

If multiple heterogeneous CPUs are used for parallel processing, then processing capability is improved, but system complexity and communication overhead increase

Engineering Contradiction:
Improveprocessing capabilityVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent employs multiple homogeneous CPU cores instead of heterogeneous CPUs. These identical cores execute the same instruction set and have the same architectural characteristics, which simplifies system design and reduces communication overhead while still enabling parallel processing capability.

Inventive Principle:
Principle #33Homogeneity

Solution Approach 2:

Each CPU core is designed to be universal and can execute any type of process instruction. The cores are not specialized for specific tasks but can handle both real-time and non-real-time processes, allowing flexible task allocation and reducing the need for specialized communication protocols between different types of processors.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Device complexity

If real-time and non-real-time processes are mixed on the same core, then device complexity is reduced, but real-time processing responsiveness deteriorates

Engineering Contradiction:
Improveprocess managementVSAvoidscheduling delay
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent segments process management by dedicating specific CPU cores exclusively to real-time processes and other cores to non-real-time processes. This physical separation eliminates context switching and scheduling delays for real-time tasks, ensuring deterministic response times while keeping process management straightforward through clear core assignment.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8416430B2Information processing apparatus
Publication Date: 2013.04.09 KONICA MINOLTA BUSINESS TECH INC
  • US8416430B2 patent drawing
  • US8416430B2 patent drawing
  • US8416430B2 patent drawing

AI summary

Disclosed is an information processing apparatus in which various kinds of information are processed in either the real time processing mode or the non-real time processing mode. The apparatus includes an operation display section to accept an inputted instruction, an image processing section to apply a processing to image information and a processor provided with a plurality of same cores. The real-time processing unnecessary process that is related to the operation display section, is fixed onto one of the plurality of same cores so that the one of the plurality of same cores is in charge of controlling the real-time processing unnecessary process, while, the real-time processing necessary process that is related to the image processing section, is fixed onto another one of the plurality of same cores so that the other one of the plurality of same cores is in charge of controlling the real-time processing necessary process.