Multi-Core CPU Protection for Protocol-Aware Packet Prioritization

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Solution Overview

Problem

Current CPU protection methods in multi-core network devices often drop both attack and normal messages, leading to impaired user experience due to insufficient protection policies when CPU utilization is high, especially affecting important messages in multi-core systems.

Innovation Solution

A method and device that differentiate between normal and special protocols based on user-assigned importance, employing distinct protection policies to prioritize the processing of special protocols and manage CPU resources by transferring or rate-limiting messages, ensuring that important messages are not dropped and user experience is improved.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single shared buffer pool is used for packet buffering in multi-core network devices, then device complexity is reduced, but CPU performance degradation occurs due to lock operations and cache invalidation

Engineering Contradiction:
Improvebuffer management complexityVSAvoidCPU processing throughput
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The shared buffer pool is segmented into multiple buffer pools, with each buffer pool assigned to a specific CPU core. This segmentation eliminates the need for lock operations when multiple cores access buffers simultaneously, as each core operates independently on its own buffer pool while still providing isolated memory regions for inter-core communication.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Isolated memory regions serve as intermediaries between different buffer pools and CPU cores. These regions enable inter-core communication and data sharing without requiring locks, as they are specifically designed for controlled access between cores while maintaining the independence of individual buffer pools.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If lock operations are used to protect shared buffer access in multi-core systems, then data consistency is maintained, but CPU performance degrades due to lock overhead and cache invalidation

Engineering Contradiction:
Improvedata consistencyVSAvoidCPU processing throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By segmenting the shared buffer into multiple isolated buffer pools assigned to different CPU cores, the system maintains data consistency within each buffer pool without requiring lock operations. Each core has exclusive access to its assigned buffer pool, eliminating the need for locks while preserving data integrity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The design creates isolated copies of buffer memory regions for each CPU core, with separate physical memory allocations. This copying approach allows each core to operate on its own buffer copy without interfering with other cores, maintaining consistency without lock overhead.

Inventive Principle:
Principle #26Copying

3Quantity of substance

If a large shared buffer pool is allocated for all CPU cores, then buffer availability is improved, but memory access efficiency decreases due to cache conflicts and false sharing

Engineering Contradiction:
Improvebuffer memory capacityVSAvoidmemory access speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The large shared buffer pool is segmented into multiple smaller buffer pools, each assigned to a specific CPU core. This segmentation ensures that each core accesses memory locally without causing cache conflicts or false sharing with other cores, while the total buffer capacity across all pools maintains the required memory availability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each CPU core is assigned a dedicated buffer pool with local memory allocation, optimizing memory access speed for each core. The local quality of memory access is improved by eliminating cross-core cache conflicts, while the aggregate buffer capacity across all local pools maintains sufficient buffer availability for the entire system.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP3232608B1CPU protection method and apparatus in multi-core network device
Publication Date: 2020.01.01 ZTE CORP
  • EP3232608B1 patent drawingFigure 1
  • EP3232608B1 patent drawingFigure 2~3
  • EP3232608B1 patent drawingFigure 4

AI summary

At least some embodiments of disclosure disclose a method and device for CPU protection in a multi-core network device. The method includes: a protection type for each network protocol is configured, the protection type including a normal protocol and a special protocol; a CPU resource utilization rate of a data core is regularly calculated, and, when the CPU resource utilization rate reaches a preset data core CPU protection execution threshold, whether the CPU resource utilization rate of the normal protocol in the data core is greater than a preset minimum guarantee execution threshold of the normal protocol is detected; when the CPU resource utilization rate of the normal protocol in the data core is greater than the preset minimum guarantee execution threshold of the normal protocol, a preset normal protocol protection policy is employed to process at least one message of the normal protocol; when the CPU resource utilization rate of the normal protocol in the data core is not greater than a preset minimum guarantee execution threshold of the normal protocol, a preset special protocol protection policy is employed to process a message of the special protocol. The disclosure processes the at least one message of the normal protocol preferentially in a case where the CPU utilization rate is too high, thereby to the maximum extent guaranteeing that important messages are not dropped and improving the user experience in the circumstance of guaranteeing a well protection effect on the CPU.