Multi-Core DSP Sync for Coherent Shared-Memory Data Transfer

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Solution Overview

Problem

Existing control systems face disruptions in signal transfer due to multiple CPUs attempting to write to a common memory, leading to data collisions and potential incorrect system operations.

Innovation Solution

A digital signal processor (DSP) is configured to synchronize data transfer between CPU cores using a shared memory, ensuring coherent data transfer and avoiding memory access collisions by aligning CPU cycles and utilizing flags to indicate data availability and access permissions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple CPUs write to a common memory simultaneously, then data transfer speed increases, but data collisions occur and system reliability deteriorates

Engineering Contradiction:

Improvedata transfer speedVSAvoiddata integrity

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The system performs preliminary synchronization actions by aligning CPU cycles and setting up access protocols before data transfer occurs. The producing CPU and consuming CPU synchronize their operation cycles in advance, establishing a predetermined pattern of when each CPU can access shared memory, thereby preventing collisions before they happen

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary synchronization mechanism that mediates between the producing CPU and consuming CPU. This intermediary system coordinates access to shared memory by controlling when each CPU can read or write, acting as a mediator that prevents direct conflicts while enabling efficient data transfer

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If CPU cycles are synchronized to prevent data collisions, then data integrity is maintained, but system complexity increases

Engineering Contradiction:

Improvedata integrityVSAvoidsynchronization mechanism complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The system implements periodic synchronization where CPU cycles are aligned in regular, repeating patterns. The producing and consuming CPUs operate in synchronized cycles that repeat predictably, creating a rhythmic pattern of data production and consumption that simplifies the synchronization logic while maintaining data integrity

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent changes operational parameters by adjusting CPU frame rates and cycle timings to achieve synchronization. By modifying these temporal parameters, the system establishes coordinated access patterns to shared memory without requiring complex hardware intervention, thereby maintaining reliability while controlling complexity

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12585522B2Systems and methods for coherent data transfer with sync in a multiple core processor

Publication Date: 2026.03.24 WOODWARD INC

AI summary

Methods and systems for a digital signal processor (DSP) to transmit data between a first central processing unit (CPU) core (a producing core) and a second CPU core (a consuming core). The first and second CPU cores are time-aligned, such that cycles of one or more frames of the first CPU core correlate to one or more cycles of the second CPU core. The first and second CPU cores are configured to access a shared memory, through which data can be written and/or read by the first and second CPU cores.