Multi-Core Processor Fault Localization Using Running Exceptions

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Solution Overview

Problem

Current methods are inadequate for quickly and accurately identifying faulty computing cores in multi-core processors, leading to user experience issues and increased return rates due to automatic restarts, particularly in mobile devices, as professional inspections are required.

Innovation Solution

A method utilizing a dynamic scheduling policy, such as a completely fair scheduler, to analyze consecutive running exceptions and determine faulty computing cores by identifying cores with a preset quantity of exceptions, and optionally shielding them to prevent further issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If professional factory inspection with special tools and manual analysis is used to detect computing core faults, then detection accuracy is improved, but inspection time and complexity increase significantly

Engineering Contradiction:
Improvefault detection accuracyVSAvoidinspection time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by recording running exception information and core correspondence information in advance during device operation. When a fault occurs, the system can immediately query and analyze the pre-recorded log files to identify the faulty core, eliminating the need for time-consuming professional inspections with special tools.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent creates a copy of the fault detection capability by using software-based log recording and analysis systems that mirror the functionality of professional factory inspection tools. This allows authorized maintenance sites to perform accurate fault detection without requiring specialized hardware or expert manual analysis.

Inventive Principle:
Principle #26Copying

2Measurement precision

If professional factory inspection with special tools and manual analysis is used to detect computing core faults, then detection accuracy is improved, but device complexity and resource requirements increase

Engineering Contradiction:
Improvefault detection accuracyVSAvoidinspection system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent replaces complex professional inspection systems with a simplified software-based solution that records and analyzes log files. This copying approach maintains detection accuracy while eliminating the need for special tools and manual expert analysis, significantly reducing system complexity.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The system implements self-service by automatically recording running exceptions and their corresponding core information in log files. The fault detection process becomes self-contained, requiring no external professional intervention or complex inspection equipment, thereby reducing device complexity.

Inventive Principle:
Principle #25Self-service

3Productivity

If dynamic scheduling policy is used to allocate program instructions to computing cores, then system productivity is improved, but difficulty in locating faulty cores increases

Engineering Contradiction:
Improvesystem throughputVSAvoidfault localization difficulty
Core Design Contradiction:
ProductivityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent implements feedback by recording the correspondence between running exceptions and computing core information in log files. This feedback mechanism allows the system to trace back from observed faults to the specific cores that executed the problematic instructions, even under dynamic scheduling, thereby maintaining fault localization capability while preserving scheduling flexibility.

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP4020215B1Method for determining fault computing core in multi-core processor and electronic device
Publication Date: 2025.11.26 HUAWEI TECH CO LTD
  • EP4020215B1 patent drawingFigure 1
  • EP4020215B1 patent drawingFigure 2
  • EP4020215B1 patent drawingFigure 3

AI summary

A method for determining a faulty computing core in a multi-core processor and an electronic device are provided. The method is applied to an electronic device configured with a multi-core processor. The multi-core processor is integrated with a plurality of computing cores, the plurality of computing cores are independent of each other, and the plurality of computing cores include a first computing core. When the electronic device runs, at least one computing core in the plurality of computing cores executes program instructions. The program instructions are allocated based on a dynamic scheduling policy. The method includes: determining a computing core corresponding to each of N running exceptions, where the running exception is caused by an exception that occurs when any computing core in the plurality of computing cores executes the program instructions (301); and when a quantity of running exceptions corresponding to the first computing core in the N running exceptions is greater than or equal to M, determining that the first computing core is a faulty computing core, where M is a preset value (303).