Multicore Idle Transition via No-Op Throttling
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Solution Overview
Problem
Multicore systems face challenges in managing sudden power surges when cores transition from idle to operational mode due to simultaneous activation of components, which can lead to voltage drops and performance issues, as conventional bulk capacitors may not adequately address these surges.
Innovation Solution
The solution involves gradually transitioning cores from idle to operational mode by inserting No-Op commands among actual instructions, which throttle performance and reduce power consumption, preventing sudden power surges by gradually increasing core activity over time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple cores transition from idle mode to full operation simultaneously, then system productivity is improved, but sudden power surge occurs causing voltage drops and performance issues
Solution Approach 1:
The transition from idle to operational mode is segmented into multiple stages with different performance levels (e.g., 25%, 50%, 75%, 100%). Cores progress through these stages sequentially rather than jumping directly to full operation, which distributes the power consumption over time and prevents sudden power surges while still achieving full productivity eventually.
2Power
If bulk capacitors are used to address power surges, then power surge mitigation is improved, but device complexity and implementation constraints increase
Solution Approach 1:
The patent replaces the mechanical/electrical solution of using bulk capacitors with a software/control-based solution. By inserting No-Op commands to throttle core performance during transition, the system mitigates power surges through logical control rather than physical energy storage components, thereby reducing device complexity and avoiding implementation constraints related to capacitor selection and placement.
3Loss of time
If cores transition quickly to operational mode, then response time is improved, but voltage supply drops occur impacting system performance
Solution Approach 1:
The system dynamically adjusts core performance based on power conditions. During transition, cores operate at variable performance levels (25%, 50%, 75%, 100%) rather than a fixed state. This dynamic approach allows the system to respond quickly to workload demands while adapting power consumption to available supply capacity, preventing voltage drops and maintaining reliability throughout the transition process.
Data Source
AI summary
A system includes a plurality of cores. Each core includes a processing unit, an on-chip memory (OCM), and an idle detector unit. Data is received and stored in the OCM. Instructions are received to process data in the OCM. The core enters an idle mode if the idle detector unit detects that the core has been idle for a first number of clocking signals. The core receives a command to process when in idle mode and transitions from the idle mode to an operational mode. A number of no operation (No-Op) commands is inserted for each time segment. A No-Op command prevents the core from processing instructions for a certain number of clocking signals. A number of No-Op commands inserted for a first time segment is greater than a number of No-Op commands inserted for a last time segment. After the last time segment no No-Op command is inserted.