Multi-Core Application Image Mapping for Faster Secure Boot

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Solution Overview

Problem

Computer systems with multiple processing cores face memory capacity inefficiencies and delayed boot sequences due to the need for significant internal memory capacity and security checks that cause processing cores to idle, reducing performance.

Innovation Solution

A combined application image is created by consolidating multiple application images for multiple processing cores, including a mapping segment, which is streamed to a security module for parallel loading and security operations, reducing memory requirements and enhancing processing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple application images are stored separately in internal memory for each processing core, then each core can execute its instructions, but internal memory capacity is significantly reduced (up to 50%)

Engineering Contradiction:
Improveinternal memory capacityVSAvoidboot sequence speed
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent segments the boot process into distinct phases: (1) loading only the combined application image header and mapping segment to internal memory, (2) streaming the full combined application image directly from external memory to each processing core's execution memory, and (3) using the mapping segment to guide core-specific instruction allocation. This segmentation eliminates the need to store complete application images in internal memory while maintaining boot performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a mapping segment as an intermediary data structure that resides in internal memory and contains metadata about the combined application image segments. This mapping segment acts as a guide that enables processing cores to locate and load their specific instruction portions directly from external memory without requiring the entire application image to be pre-loaded into internal memory.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If security checks are performed on program instructions during boot, then system security is verified, but processing cores must wait idly causing boot sequence delays

Engineering Contradiction:
Improvesecurity verificationVSAvoidboot sequence time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs security verification on the combined application image header and mapping segment before the main processing cores begin their boot operations. By completing security checks on these critical components in advance, the system ensures security requirements are met while allowing processing cores to simultaneously proceed with loading and executing their respective instruction segments without idle waiting time.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent enables continuous boot operations by overlapping security verification with instruction loading and execution. While security checks are performed on the combined application image, processing cores continuously load their specific instruction portions from external memory and begin execution without interruption. This eliminates idle waiting periods and maintains continuous productive action throughout the boot sequence.

Inventive Principle:
Principle #20Continuity of useful action

3Quantity of substance

If application images are consolidated into a single combined image, then memory capacity requirements are reduced, but the system must handle complex mapping and segmentation

Engineering Contradiction:
Improvememory capacityVSAvoidmapping and segmentation complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent implements self-service mechanisms where the mapping segment contains self-describing metadata that automatically identifies segment boundaries, sizes, and associations with specific processing cores. This self-describing structure enables the system to automatically parse and allocate instructions without requiring complex external management logic, thereby reducing the perceived complexity despite the consolidated image format.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent changes the organizational parameters of application images by consolidating multiple separate images into a single combined image with a standardized segment structure. Each segment within the combined image is marked with metadata parameters that identify its purpose, target processing core, and memory allocation requirements. This parameter-based organization simplifies the management complexity compared to handling multiple separate image files.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20260010378A1Enhanced boot sequence using multi-core application images
Publication Date: 2026.01.08 TEXAS INSTRUMENTS INC
  • US20260010378A1 patent drawing
  • US20260010378A1 patent drawing
  • US20260010378A1 patent drawing

AI summary

In an example embodiment, a method is provided for combining multiple application images into a combined application image for improved boot processes. The method includes identifying multiple application images corresponding to multiple processing cores of a computer system, each including a set of application code segments corresponding to a respective processing core of the multiple processing cores, generating a combined application image based on the multiple application images, the combined application image including a set of application code segments corresponding to the set of application code segments of each application image of the multiple application images, and a mapping segment indicative of correlations between the set of application code segments of the combined application image and the set of application code segments of each application image, and storing the combined application image on an external memory external relative to the computer system.