Multicore Interferer Generation for Deterministic Processor Testing

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Solution Overview

Problem

Multicore processors often result in non-deterministic operations, which can lead to increased execution time and failure to meet real-time requirements, particularly in applications like aviation operations, where determinism is crucial.

Innovation Solution

An automated framework generates processor-specific interferers to test and characterize multicore determinism, ensuring deterministic and repeatable interference testing, with configurable parameters and post-processing analysis to identify worst-case latencies and deviations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple processor cores are used, then processing capacity and productivity are improved, but operational determinism deteriorates leading to non-deterministic behavior

Engineering Contradiction:

Improveprocessing capacityVSAvoidoperational determinism

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent segments the testing process into distinct phases: generating interferer code for each core, executing tests with controlled interference, and analyzing results separately. This segmentation allows systematic characterization of each core's behavior under interference while maintaining overall test determinism.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by generating interferer code and configuring test parameters before actual execution. The framework pre-defines interference scenarios, test cases, and evaluation criteria, enabling deterministic replay and consistent results across multiple test runs.

Inventive Principle:

Principle #10Preliminary action

2Speed

If multiple processor cores are used, then processing speed is improved, but execution time variability increases causing real-time requirements to fail

Engineering Contradiction:

Improveprocessing speedVSAvoidexecution time variability

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The patent implements feedback mechanisms by measuring execution times under various interference conditions and using this data to characterize worst-case scenarios. The framework collects performance data, compares it against thresholds, and adjusts test parameters to comprehensively evaluate timing behavior.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent systematically changes test parameters including interference intensity, core activation patterns, and workload characteristics to characterize processor behavior across different operating conditions. This enables identification of worst-case execution times under controlled parameter variations.

Inventive Principle:

Principle #35Parameter changes

3Measurement precision

If manual testing methods are used for processor characterization, then test accuracy is maintained, but time consumption and productivity are reduced

Engineering Contradiction:

Improvetest accuracyVSAvoidtime consumption

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent creates copies of test code and interferer patterns that can be automatically generated and executed across multiple cores. The framework replicates test scenarios systematically, enabling comprehensive coverage without manual intervention for each test case.

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The testing framework performs self-service by automatically generating test cases, configuring interferers, executing tests, and analyzing results without requiring manual setup for each test scenario. The system manages its own test workflow, significantly reducing engineering time while maintaining accuracy.

Inventive Principle:

Principle #25Self-service

4Productivity

If processor-specific interferers are generated automatically, then testing efficiency is improved, but test complexity and device complexity increase

Engineering Contradiction:

Improvetesting efficiencyVSAvoidtest framework complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent creates a universal testing framework that can characterize multiple processor cores and different interferer types through a single unified system. The framework handles various processor architectures, interference patterns, and test scenarios using common infrastructure, reducing overall complexity despite increased capabilities.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260003760A1Multicore interferer generation

Publication Date: 2026.01.01 GENERAL ELECTRIC CO

AI summary

A system for multi-core interferer generation includes a processor and a memory including instructions which, when executed by the processor, cause the system at least to perform generating an interference test for one or more processor cores based upon one or more configuration files; introducing interference to the one or more processor cores to generate one or more interference test results; and filtering the one or more test results by evaluating performance data against one or more expected result hypotheses, each defining benchmark execution behavior and tolerance thresholds.