Multicore Interrupt Register Banks for Bus Collision Reduction
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Solution Overview
Problem
Multicore processing systems face challenges such as communications bus collisions, interrupt management complexity, and context-awareness issues due to shared peripheral access and interrupt handling across multiple cores in camera control systems of mobile devices.
Innovation Solution
A multicore processor architecture with dedicated interrupt register banks and communication bridges for each core, allowing individual configuration and access to shared peripherals, and time-partitioning of communications to minimize bus arbitration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple cores share access to a common peripheral block, then resource utilization is improved, but bus collisions and communication overhead increase
Solution Approach 1:
The interrupt controller is segmented into multiple independent interrupt register banks, with each bank dedicated to a specific core. This segmentation allows each core to have its own interrupt configuration space, eliminating bus collisions when accessing interrupt registers while still enabling shared peripheral access through the common interrupt controller structure.
2Ease of operation
If interrupt registers are duplicated for each core, then interrupt management is simplified, but device complexity increases
Solution Approach 1:
The interrupt controller serves as an intermediary between the shared peripheral blocks and multiple cores. It provides a unified interface that manages interrupt generation and routing, while the separate interrupt register banks provide simple, dedicated configuration access for each core. This intermediary structure simplifies interrupt management for each core without requiring full duplication of the entire interrupt controller.
3Productivity
If a core accesses a peripheral block not designated to its domain, then resource utilization is improved, but communication bus stalls occur
Solution Approach 1:
The system performs preliminary configuration by assigning specific peripheral blocks to specific core domains in advance. The interrupt controller is configured with domain assignments that pre-establish which cores can access which peripherals without causing bus stalls. This preliminary setup allows efficient resource utilization while preventing communication bus conflicts.
Data Source
AI summary
A multicore processor may include a plurality of cores including at least a first core and a second core, a shared peripheral comprising a plurality of interrupt register banks including at least a first interrupt register bank dedicated to the first core and a second interrupt register bank dedicated to the second core, and a plurality of communications bridges, including at least a first bridge interfaced between the first core and the shared peripheral and at least a second bridge interfaced between the second core and the shared peripheral. The first core may be configured to program the first interrupt register bank via the first bridge to configure the shared peripheral for access by the first core. The second core may be configured to program the second interrupt register bank via the second bridge to configure the shared peripheral for access by the second core.