Multi-Core LDPC Decoding Using Base Graph Segmentation

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Solution Overview

Problem

Decoding data encoded with low density parity check codes requires significant memory and processing resources, particularly when using soft decoding algorithms, which is a challenge in communications protocols like 5G New Radio.

Innovation Solution

The use of a processor with multiple cores that perform partial decoding operations on compacted representations of base graphs and lifting sets, employing message passing algorithms and belief propagation to efficiently decode LDPC codes, reducing the computational load by distributing decoding tasks across multiple cores.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If soft decoding algorithms are used for LDPC codes, then decoding accuracy is improved, but memory and processing resources are significantly increased

Engineering Contradiction:
Improvedecoding accuracyVSAvoidmemory and processing resources
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent divides the LDPC code decoding task into multiple independent parts by using a base graph with lifting. The base graph is segmented into smaller units that can be processed independently through parallel operations, reducing the memory and computational complexity required for soft decoding while maintaining decoding accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transforms the decoding problem from a two-dimensional matrix operation into a three-dimensional structure using base graphs and lifting operations. This dimensional transformation enables more efficient memory access patterns and parallel processing, reducing the overall computational burden of soft decoding algorithms.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If complex parity check codes are used in communications protocols, then error correction capability is improved, but decoding computational load is increased

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddecoding computational load
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the complex parity check code into a base graph structure with lifting, allowing the error correction capability to be maintained while enabling parallel processing of code blocks. This segmentation reduces the computational load per processing unit and enables scalable decoding for high-rate LDPC codes used in 5G New Radio.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by pre-defining the base graph structure and lifting parameters before actual decoding. This preparation phase allows the decoding process to proceed more efficiently by avoiding complex real-time calculations, thus reducing the computational load while maintaining high error correction capability.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If traditional decoding methods are used for high-rate LDPC codes, then decoding accuracy is maintained, but memory requirements are significantly increased

Engineering Contradiction:
Improvedecoding accuracyVSAvoidmemory requirements
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent segments the large parity check matrix into a compact base graph with lifting parameters, dramatically reducing the memory storage requirements. The base graph approach represents the same decoding information in a compressed form, enabling traditional decoding accuracy to be maintained with significantly reduced memory footprint suitable for 5G implementations.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240430037A1Parity check decoding
Publication Date: 2024.12.26 NVIDIA CORP
  • US20240430037A1 patent drawing
  • US20240430037A1 patent drawing
  • US20240430037A1 patent drawing

AI summary

Apparatuses, systems, and techniques to decode encoded data. In at least one embodiment, parts of information for decoding the encoded data is provided to a plurality of processors, and parts of data decoded by the plurality of processors is combined.