Multi-Core LDPC Decoding with Scheduled Inter-Core Message Passing
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Solution Overview
Problem
Current LDPC decoding processes in wireless communication networks, particularly on GPUs and TPUs, face performance bottlenecks due to inefficient data transfer and cache usage, leading to suboptimal performance when handling large check node degrees and extensive bus system utilization.
Innovation Solution
Implementing a method that distributes demodulated signal inputs across multiple processing cores and schedules message passing between them to minimize bus usage, allowing for efficient decoding by performing computations within cores and limiting full iterations according to a set schedule.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If classic message passing decoding is implemented on GPUs/TPUs, then decoding capability is achieved, but bus usage increases and performance bottlenecks occur
Solution Approach 1:
The patent divides the decoding graph into multiple communities or groups, where each group is assigned to a separate processing core. This segmentation reduces the need for inter-core communication over the bus system, as message passing is minimized between cores while maintaining decoding functionality within each core's local group.
Solution Approach 2:
The patent introduces a new dimension of parallel processing by utilizing multiple processing cores simultaneously, each handling a subset of the decoding operations. This multi-core architecture transforms the single-threaded decoding process into a parallel system, improving throughput while reducing bus contention through localized processing.
2Productivity
If multiple processing cores are used for decoding, then processing capacity increases, but bus system utilization increases leading to bottlenecks
Solution Approach 1:
By segmenting the decoding workload into distinct communities assigned to different cores, the patent reduces inter-core communication requirements. Each core processes its local community independently, minimizing the need for complex bus system coordination and data transfer between cores.
Solution Approach 2:
The patent introduces a schedule or coordination mechanism that acts as an intermediary to manage message passing between cores. This mediator optimizes the timing and necessity of inter-core communication, reducing unnecessary bus transactions while maintaining correct decoding semantics.
3Reliability
If full message passing iterations are performed between cores, then decoding accuracy is maintained, but decoding time increases
Solution Approach 1:
The patent performs message passing only between specific communities or groups of nodes rather than complete full iterations across all cores. This partial action approach maintains sufficient decoding accuracy for the processed subsets while significantly reducing the total number of inter-core communication rounds required.
Solution Approach 2:
The patent performs preliminary decoding operations within each core's local community before engaging in inter-core message passing. This preliminary processing reduces the amount of data and iterations needed for subsequent inter-core communication, thereby reducing overall decoding time while maintaining accuracy.
Data Source
AI summary
Embodiments herein relate to a method performed by a network node for handling a received signal in a communication network. The network node distributes a first number of inputs of a demodulated signal to a first processing core of at least two processing cores and a second number of inputs of the demodulated signal to a second processing core of the at least two processing cores. The network node further decodes the first number of inputs of the demodulated signal by a first message passing within the first processing core, and decodes the second number of inputs of the demodulated signal by a second message passing within the second processing core. The network node further decodes the demodulated signal by performing a third message passing between the different processing cores over a bus that is performed according to a set schedule.