Multi-Core Self-Test Scheduling for Power-Stable MBIST
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Solution Overview
Problem
Multi-core processing circuits face power instability during self-testing due to simultaneous activation of multiple core-processing circuits, leading to false test results and reduced yield, as the power drop affects signal levels.
Innovation Solution
A power-stabilizing test mechanism is implemented using a self-test scheduling circuit that activates memory built-in self-test circuits of each core-processing unit sequentially with a signal handshake process, maintaining an average power draining amount within a predetermined range to prevent large voltage drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple core-processing circuits are activated simultaneously for self-test, then test efficiency is improved, but power stability deteriorates causing false test results
Solution Approach 1:
The self-test process is segmented into sequential phases, with each core-processing circuit tested individually rather than simultaneously. The self-test scheduling circuit activates one core-processing circuit at a time, dividing the overall test process into discrete time segments where only a single circuit consumes high power during its test window, thereby maintaining power stability while still achieving comprehensive testing of all cores
Solution Approach 2:
The self-test process employs periodic activation of core-processing circuits, where each core is activated for testing at regular intervals determined by the delay time parameter. This periodic action ensures that power consumption remains within predetermined ranges during each test cycle, preventing the simultaneous power surge that would occur with parallel testing while maintaining systematic coverage of all circuits
2Loss of time
If simultaneous self-test is performed by multiple circuits, then test time is reduced, but signal level accuracy deteriorates due to power drop
Solution Approach 1:
The self-test scheduling circuit incorporates feedback mechanisms to monitor power consumption levels and adjust the activation timing of core-processing circuits accordingly. By detecting when power consumption approaches predetermined thresholds, the scheduling circuit dynamically controls the activation sequence, ensuring that test operations proceed only when power levels are stable enough to maintain accurate signal measurements, thus preventing false test results caused by power-induced signal level variations
Data Source
AI summary
The present disclosure discloses a multi-core processing circuit having power-stabilizing test mechanism that includes a plurality of core-processing circuits arranged in an order and a self-test scheduling circuit. Each of the core-processing circuits includes a memory built-in self-test circuit. The self-test scheduling circuit receives a main activation signal to activate the memory built-in self-test circuit of one of the core-processing circuits every delay time in the order based on signal handshake to perform self-test, wherein one of the activated core-processing circuits has a largest average power draining amount in a predetermined range within the delay time.