Multicore Software Architecture With Alternating Shared Memory Access
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Solution Overview
Problem
Current multicore processors in safety-critical domains like aviation face non-deterministic operations due to shared resources, which hinder certification for aviation operations.
Innovation Solution
A software architecture that mitigates interference by using a single core for peripheral control, implementing a shared memory access mechanism with alternating time intervals, and ensuring core synchronization through frame-based frequency matching and overframe detection, along with dedicated memory access and inadvertent access detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processor cores are used to increase processing capability, then productivity is improved, but deterministic execution is lost due to shared resources causing non-deterministic operations
Solution Approach 1:
The patent segments shared resources into core-private resources. Each processor core is assigned dedicated cache memory and memory controllers, eliminating shared resource contention. This segmentation allows multiple cores to operate in parallel (improving productivity) while each core has predictable access to its private resources (maintaining deterministic execution).
Solution Approach 2:
The patent introduces a hierarchical memory architecture that adds a new dimension to resource organization. By implementing L1, L2, and L3 cache levels with selective sharing, the system moves from flat resource sharing to multi-level resource hierarchy, enabling both parallel processing and deterministic memory access patterns.
2Reliability
If multiple processor cores are deactivated to ensure deterministic execution, then deterministic execution is improved, but productivity is reduced due to underutilization of processing capability
Solution Approach 1:
Instead of deactivating cores, the patent segments resources so that all cores can remain active with dedicated private resources. Each core has its own cache and memory controllers, allowing full utilization of processing capability while maintaining deterministic execution characteristics.
Solution Approach 2:
The patent implements local quality by giving each core private cache memory and memory controllers tailored to its specific needs. This local resource allocation allows each active core to operate deterministically without interfering with others, enabling full productivity while maintaining reliability.
3Productivity
If shared memory access is implemented to enable multicore processing, then productivity is improved, but interference between cores causes non-deterministic operations
Solution Approach 1:
The patent segments memory resources into core-private L1 caches and shared L2/L3 caches. This segmentation reduces interference by minimizing simultaneous access to the same memory resources, allowing multicore processing while maintaining deterministic memory access patterns.
Solution Approach 2:
The patent implements periodic memory access patterns where cores access shared memory in alternating time slots or frames. This periodic action allows shared memory to be accessed by multiple cores without simultaneous interference, maintaining both productivity and deterministic execution.
Data Source
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AI summary
A system for multi-core deterministic processing includes a processor (420) and a memory (430) comprising instructions which, when executed by the processor, cause the system to synchronize a first processor core (core 0) and a second processor core (core 1) in time for alternating access to a first shared memory (global RAM #1) and a second shared memory (global RAM #2). During a first time frame, the first processor core accesses the first shared memory and the second processor core accesses the second shared memory. During a second time frame, the first processor core accesses the second shared memory and the second processor core accesses the first shared memory. The system may further include dedicated memory (RAM #1, RAM #2) associated with each core, a third processor core (core n) with corresponding memory (RAM #z, global RAM #x), and support for communication and I/O peripherals. The architecture mitigates memory access interference by applying alternating memory access intervals to ensure deterministic operation in safety-critical systems.