Multicore Memory Scheduling for Deterministic Execution
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Solution Overview
Problem
Current multicore processors used in safety-critical domains like aviation face non-deterministic operations due to shared resources, which hinder certification for aviation operations.
Innovation Solution
A software architecture that mitigates interference by using a single core for peripheral control, implementing a shared memory access mechanism with alternating time intervals, and ensuring core synchronization through frame-based frequency matching and overframe detection, along with dedicated memory regions and a single external peripheral controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processor cores are used to increase processing capability, then productivity is improved, but deterministic execution is worsened due to non-deterministic operations from shared resources
Solution Approach 1:
The patent divides the processor into separate functional units: a single dedicated core for peripheral control and multiple application cores for processing. This segmentation isolates the deterministic peripheral control functions from the parallel processing functions, allowing the system to maintain determinism in critical I/O operations while benefiting from parallel processing capability.
Solution Approach 2:
The patent introduces a single core acting as an intermediary between peripheral devices and multiple application cores. This intermediary core manages all peripheral access and synchronization, mediating communication between cores and external devices to ensure deterministic timing and prevent race conditions.
2Reliability
If a single core is dedicated to peripheral control to ensure deterministic execution, then reliability is improved, but device complexity increases due to additional synchronization mechanisms
Solution Approach 1:
The patent combines multiple synchronization functions into a single integrated core that handles peripheral control, timing, and coordination for all application cores. By merging these functions into one dedicated unit, the system reduces the overall complexity compared to having separate synchronization mechanisms for each core.
Solution Approach 2:
The single peripheral control core is designed with multi-functionality, handling I/O operations, timing control, synchronization signals, and coordination tasks all within one core. This universal design reduces the need for separate dedicated hardware components for each function.
Data Source
AI summary
A system for multi-core deterministic processing includes a processor and a memory including instructions which, when executed by the processor, cause the system at least to perform synchronizing a first processor core and a second processor core in time for access to a first shared memory and a second shared memory; causing, by the system, accessing by the first processor core of the first shared memory in a first time frame; causing, by the system, accessing by the second processor core of the second shared memory in the first time frame; causing, by the system, accessing by the first processor core of the second shared memory in a second time frame; and causing, by the system, accessing by the second processor core of the first shared memory in the second time frame.