Multicore Processor Memory Partitioning for Deterministic Data Processing
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Solution Overview
Problem
Existing multicore processor systems face challenges in ensuring deterministic data processing, particularly in safety-critical applications like aviation, due to unpredictable memory access and resource contention, leading to conservative execution time estimates and inefficient resource utilization.
Innovation Solution
A multicore processor system with an intermediate storage assigned to each processor, which stores information elements for deterministic data processing prior to execution, reducing resource contention and enabling static time analysis, and incorporating a state and control logic to manage page pools for efficient and deterministic data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If arbitration logic is used to determine exclusive access to shared resources, then resource access control is improved, but program execution of other requestors is blocked
Solution Approach 1:
The patent segments memory resources into private memory regions (L3 cache partitions) assigned to each processing core and shared memory regions. This segmentation allows each core to have dedicated storage space that does not require arbitration, eliminating blocking while maintaining resource control through defined access boundaries.
Solution Approach 2:
The patent implements preliminary action by pre-allocating private memory regions to each processing core before execution. This allows cores to immediately access their designated memory space without waiting for arbitration, while shared resources are accessed only when necessary through controlled interfaces.
2Reliability
If conservative upper execution time limits are used for high-integrity applications, then safety requirements are met, but available processing resources cannot be fully utilized
Solution Approach 1:
The patent segments applications into high-integrity and low-integrity categories, assigning them to different processing cores with dedicated private memory regions. This isolation allows high-integrity applications to meet conservative timing requirements while low-integrity applications can utilize remaining resources, achieving both safety and resource utilization.
Solution Approach 2:
The patent applies local quality by providing different memory access characteristics to different cores based on their application requirements. High-integrity cores receive guaranteed access to private memory regions with predictable timing, while other cores can utilize shared resources with variable access patterns, optimizing overall system performance.
3Reliability
If applications are separated according to integrity level and processor, then safety certification is simplified, but the number of processors required increases
Solution Approach 1:
The patent segments the memory hierarchy into private and shared regions, allowing multiple integrity levels to coexist on the same multicore processor. High-integrity applications run on dedicated cores with private memory for certification simplicity, while low-integrity applications share other resources, reducing the total processor count needed.
Solution Approach 2:
The patent makes the multicore processor universal by enabling it to handle multiple integrity levels simultaneously through the private/shared memory architecture. The same physical processor can serve both safety-critical and non-critical functions, eliminating the need for separate dedicated processors for each integrity level.
4Productivity
If intermediate storage is assigned to each processor, then resource contention is reduced, but device complexity increases
Solution Approach 1:
The patent merges the intermediate storage function into the existing L3 cache structure, creating private memory regions that serve both as cache and as dedicated storage for each core. This integration avoids adding separate complexity while achieving the resource contention reduction benefits of dedicated intermediate storage.
Data Source
AI summary
A multicore processor system for deterministic data processing in a data processor includes a data processor having at least two processors, a common interface to couple the at least two processors to at least one shared main memory of the data processor and at least one common further resource of the data processor. Each processor includes a respective intermediate storage which is coupled to this processor and is arranged between the respective processor and the common interface so at least one information element for deterministic data processing in the respective processor is storable in the intermediate storage prior to this deterministic data processing. A method M for deterministic data processing in a data processor is disclosed.