Multicore Processor Memory Segmentation for ASIL Isolation
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Solution Overview
Problem
In safety-related applications, existing technologies fail to effectively separate system parts with different safety levels in multicore processors, leading to potential interference and errors.
Innovation Solution
A method is implemented where each processor core can only access its associated protected memory range, using a memory protection device to ensure that only software with a specific safety level runs on each core, preventing access to other cores' memory ranges and allowing for independent development and operation of system parts with different ASILs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If processor cores are allowed to access multiple memory ranges for versatility, then system functionality is improved, but interference between different safety levels occurs
Solution Approach 1:
The memory space is segmented into multiple protected memory ranges, each associated with a specific processor core and safety level. The memory protection device divides the address space into distinct regions that can be independently accessed only by authorized processor cores, thereby preventing interference between different safety levels while maintaining system functionality.
Solution Approach 2:
A memory protection device is introduced as an intermediary component between processor cores and memory ranges. This device mediates access requests by checking whether the requesting processor core is authorized to access the target memory range, thus enabling versatile memory access while ensuring safety level isolation.
2Reliability
If memory protection mechanisms are implemented to ensure safety level separation, then reliability is improved, but device complexity increases
Solution Approach 1:
The memory protection device is designed as a universal mechanism that handles multiple safety levels (ASIL QM, A, B, C, D) and multiple processor cores through a unified access control architecture. This multi-functional approach ensures reliability across different safety levels without requiring separate protection mechanisms for each core or memory range, thereby limiting the increase in device complexity.
3Reliability
If strict memory access control is enforced for safety levels, then freedom from interference is improved, but system productivity decreases
Solution Approach 1:
Each processor core is configured with knowledge of its authorized memory ranges through static configuration or runtime setup. The processor cores self-regulate their memory access behavior by only attempting to access memory ranges they are authorized to use, eliminating the need for continuous intervention by the memory protection device and minimizing access overhead while maintaining safety level separation.
Data Source
AI summary
A method for the coexistence of software having different safety levels in a multicore processor which has at least two processor cores (2, 3). A memory range (4, 5) is associated with each processor core (2, 3) and a plurality of software (SW1, SW2) is processed on one of the processor cores (2, 3) having a predefined safety level. The plurality of software (SW1, SW2) is processed having a predefined safety level only on the processor core (2, 3) with which the same safety level is associated, in which during the processing of the plurality of software (SW1, SW2), the processor core (2, 3) accesses only the protected memory range (4, 5) which is permanently associated with this processor core (2, 3).