Multi-Core Message Verification for In-Vehicle Arithmetic Units
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Solution Overview
Problem
Existing in-vehicle systems lack sufficient safety measures against cyber security attacks, particularly when unauthorized messages bypass initial verification in multiprocessor environments.
Innovation Solution
An arithmetic device with multiple cores (first, second, and third cores) performs dual verification processes, where the second and third cores independently verify and manage authority to protect against unauthorized messages, ensuring robustness even if initial verification is compromised.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple general-purpose computing units are used to handle diverse tasks, then versatility is improved, but device complexity increases and power consumption rises
Solution Approach 1:
The patent implements a single computing unit that can function as both a vector processing unit and a matrix processing unit through dynamic reconfiguration. The same physical computing resources are shared between different computational modes, allowing the system to handle both vector and matrix operations without requiring separate dedicated hardware for each function type.
Solution Approach 2:
The computing unit dynamically switches between vector processing mode and matrix processing mode based on the computational requirements of the current task. This dynamic reconfiguration allows the system to adapt its functional characteristics in real-time, optimizing performance for the specific operation being performed while maintaining hardware efficiency.
2Adaptability or versatility
If multiple general-purpose computing units are deployed, then task versatility improves, but power consumption increases
Solution Approach 1:
The patent employs a single computing unit that serves multiple purposes by switching between vector and matrix processing functions. This eliminates the need to power multiple separate computing units simultaneously, reducing overall power consumption while maintaining the ability to handle diverse computational tasks as needed.
Solution Approach 2:
The computing unit automatically reconfigures itself between different operational modes based on the input data type and computational requirements, without requiring external control overhead. This self-managing capability optimizes power usage by activating only the necessary processing functions for each task.
3Reliability
If vector processing and matrix processing are handled by separate units, then processing specialization improves, but device complexity and inter-unit communication overhead increase
Solution Approach 1:
The patent merges vector processing capabilities and matrix processing capabilities into a single integrated computing unit. This consolidation eliminates the need for separate hardware units and the complex communication interfaces between them, while maintaining the processing efficiency of both operation types through dedicated functional blocks within the unified architecture.
Solution Approach 2:
The computing unit is designed to perform both vector operations and matrix operations with optimized performance for each type. By incorporating specialized functional blocks for both operations within a single unit, the system achieves processing efficiency comparable to dedicated separate units without the architectural complexity and communication overhead of multiple independent units.
Data Source
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AI summary
An arithmetic device includes a first core, a second core, and one or more other cores that perform arithmetic processing. The first core includes a first verification unit that performs a first verification process on a message received from outside of the arithmetic device. The second core includes a verification destination determination processing unit that determines whether or not the second core executes the second verification process on the message based on identification information included in the message.